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Part 6: Using FPGA IP in an FPGA Application (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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In Part 5 of this tutorial, you validate whether the generated FPGA IP meets specific application requirements. In Part 6 of this tutorial, you integrate the FPGA IP to a real FPGA application. You first run this application in simulation mode to verify the results are expected, and then you can compile this application at the desired clock rate. A typical FPGA application includes the following items:

  • Host VI—Communicates with the FPGA VI by writing input data to the FPGA VI and reading output data from the FPGA VI. You can use the host VI to verify whether the associated FPGA VI is working properly. Refer to labview\examples\FPGAIPBuilder\FIR\Application\Host\FIR_HostVI.vi for a completed version of the host VI.

  • FPGA VI—Processes data received from the host VI. This VI executes on an FPGA target and includes the FPGA IP you generate in Part 4 of this tutorial. Refer to labview\examples\FPGAIPBuilder\FIR\Application\FPGA\FIR_FPGAVI.vi for a completed version of the FPGA VI. This VI contains a placeholder FPGA IP VI. You must replace the placeholder VI with the actual FPGA IP you generated in Part 4 of this tutorial.

  • DMA FIFOs—Transfers data between different host VIs and FPGA VIs. You must create the DMA FIFOs manually under the FPGA target if you need to send data from the host VIs to the FPGA VIs or vice versa. Open labview\examples\FPGAIPBuilder\FIR\FIR.lvproj and refer to the FIR_Output and FIR_Input project items under My Computer»FPGA Target»FPGA for examples of DMA FIFOs.

  • FPGA IP—Contains FPGA-optimized fixed-point algorithms or FPGA IP you generated in Part 4 of this tutorial.

Complete the following steps to integrate and use the FPGA IP.

  1. Copy the host and FPGA VIs to the directory where you saved the project in Part 5 of this tutorial.
  2. Open the project.
  3. Add the host VI under My Computer.
  4. Add the FPGA VI under My Computer»FPGA Target (PXI-7851R).
  5. Right-click FPGA Target (PXI-7851R) and select Execute VI on»Development Computer with Simulated I/O. This option enables you to run the host and FPGA VIs without compilation.
  6. Open the FPGA VI and replace the subVI, FIR_IP_Placeholder.vi, with the FPGA IP you generated in Part 4 of this tutorial.
  7. Create two DMA FIFOs under My Computer»FPGA Target (PXI-7851R).
    Note  Instead of creating the DMA FIFOs, you can drag and drop the example DMA FIFOs in the labview\examples\FPGAIPBuilder\FIR\FIR.lvproj to your project.

  8. Open the host VI and the FPGA VI, respectively, and verify they link to the correct DMA FIFOs you created in the previous step.
  9. Run the host VI.

The host VI randomly generates input data and compares the results between the original fixed-point FIR filter and the generated FPGA IP. Ensure the two results match each other. After you verify that the FPGA IP works properly in simulation mode, right-click FPGA Target (PXI-7851R) and select Execute VI on»FPGA Target from the shortcut menu and compile the FPGA VI to ensure this VI can compile at the clock rate of 200 MHz. You then can run this FPGA VI on a real FPGA target.


 

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