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Part 5: Validating Generated FPGA IP (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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In Part 4 of this tutorial, you generate FPGA IP that meets specific application requirements. However, the build report might not reflect the actual performance of the FPGA IP in an FPGA application. In Part 5 of this tutorial, you create a new VI to validate the function of the generated FPGA IP and to calculate the actual initiation interval and latency. You then create another new VI to validate the clock rate and resource usage of the FPGA IP.

Complete the following steps to validate the function, initiation interval, and latency:

  1. Open the project you saved in Part 4 of this tutorial.
  2. Right-click My Computer and select New»VI from the shortcut menu.
    Note  Instead of creating a new VI, you can add an existing VI to this project. Refer to the labview\examples\FPGAIPBuilder\FIR\Validation\FIR_Validation.vi for a completed version of the VI you can use. This VI contains a placeholder FPGA IP VI. You must replace the placeholder VI with the actual FPGA IP you generated in Part 4 of this tutorial.

  3. Add the original algorithm VI you created in Part 2 to the block diagram of this new VI.
  4. Add test data to this VI to verify that the original algorithm VI works properly.
  5. Add the FPGA IP you want to validate to the block diagram of this new VI.
  6. Wire the same test data and the handshaking signals to the FPGA IP.
  7. Add LabVIEW code to this VI to calculate the initiation interval and latency of the FPGA IP.
  8. Save and run this VI.

    Verify whether the FPGA IP can return the same results as the original algorithm VI. Also verify whether the actual initiation interval and latency values are consistent with those in the build report.
  9. Save the project.

Complete the following steps to validate the clock rate and resource usage:

  1. Open the project you saved in the previous section.
  2. Right-click FPGA Target under My Computer and select New»VI from the shortcut menu.
    Note  Instead of creating a new VI, you can add an existing VI to this project. Refer to the labview\examples\FPGAIPBuilder\FIR\Validation\FIR_Validate_Clock_Resource.vi for a completed version of the VI you can use. This VI contains a placeholder FPGA IP VI. You must replace the placeholder VI with the actual FPGA IP you generated in Part 4 of this tutorial.

  3. Place a single-cycle Timed Loop on the block diagram of this VI.
  4. Add the FPGA IP you want to validate to the single-cycle Timed Loop.
  5. Right-click the terminals of the FPGA IP and create controls and indicators for all terminals.
  6. Create an FPGA-derived clock with the desired derived frequency of 200 MHz.
  7. Connect the expected FPGA clock to the Source Name input of the single-cycle Timed Loop.
  8. Save and compile this VI.

    A successful compilation indicates that the FPGA IP can meet the clock rate requirement. In the compilation report, check the number of DSP48s and block RAM.

After you validate the FPGA IP, you use the FPGA IP in Part 6 of this tutorial.


 

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