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Owning Palette: FPGA IP Builder Functions
Requires: FPGA IP Builder. This topic might not match its corresponding palette in LabVIEW depending on your operating system, licensed product(s), and target.
Use the structures to control data flow.
|Note This palette is specific to the FPGA IP Builder and contains a subset of the VIs and functions that are on this palette when you edit a host VI.|
Refer to the Structures Palette Details topic for information about restrictions related to the objects on this palette.
|Case Structure||Has one or more subdiagrams, or cases, exactly one of which executes when the structure executes. The value wired to the selector terminal determines which case to execute and can be Boolean, string, integer, enumerated type, or error cluster. Right-click the structure border to add or delete cases. Use the Labeling tool to enter value(s) in the case selector label and configure the value(s) handled by each case.|
|Feedback Node||Stores data from one VI execution or loop iteration to the next.|
|For Loop||Executes its subdiagram n times, where n is the value wired to the count (N) terminal. The iteration (i) terminal provides the current loop iteration count, which ranges from 0 to n–1.|
|While Loop||Repeats the subdiagram inside it until the conditional terminal, an input terminal, receives a particular Boolean value. The Boolean value depends on the continuation behavior of the While Loop. Right-click the conditional terminal and select Stop if True or Continue if True from the shortcut menu. You also can wire an error cluster to the conditional terminal, right-click the terminal, and select Stop on Error or Continue while Error from the shortcut menu. The While Loop always executes at least once.|
|Decorations||Use the decorations located on the Decorations palette to group or separate objects on a block diagram with boxes, lines, or arrows. These objects are for decoration only and do not modify data.|