Power On, Reset, and Download Conditions

NI RF Vector Signal Transceivers Help

Edition Date: June 2018

Part Number: 373680F-01

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The PXIe-5646 sets some hardware circuitry to certain states at power on and at device reset. The PXIe-5646 applies certain conditions to the device state upon FPGA reset.

Power On Conditions

Power on conditions are present after powering on or restarting the system and until an FPGA VI has been uploaded to the device.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured and appear to the bus as high impedance.
  • ADCs are reset to the component default state.
  • DACs are reset to the component default state.

Reset Conditions

The following conditions apply to the device state upon FPGA reset.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured and appear to the bus as high impedance; however, reservations are maintained.
  • ADC states are maintained.
  • DAC states are maintained.
Note Note  Reset conditions apply only when using the instrument design libraries.

Download Conditions

The following conditions apply to the device state upon downloading a new FPGA VI to the PXIe-5646.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured (appear to the bus as high impedance); however, reservations are maintained.
  • ADC states are maintained.
  • DAC states are maintained.
Note Note  The Data Clock is disabled immediately after downloading a new FPGA VI to the PXIe-5646.

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