Synchronization Using NI-RFSA and NI-RFSG

NI RF Vector Signal Transceivers Help

Edition Date: June 2018

Part Number: 373680F-01

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The PXIe-5646 allows for multidevice synchronization with Sample Clock-level alignment. To perform multidevice synchronization, you must lock all devices to phase-aligned Reference Clocks. One way to do this is to specify PXI_CLK10 as the Reference Clock source for all devices. If you want to supply an external Reference Clock, some chassis allow you to override the PXI_CLK10 using an external reference input terminal on the chassis.

Alternatively, you can split the external Reference Clock with a passive power-divider or active distribution amplifier and provide a phase-aligned version to each PXIe-5646 REF IN front panel connector. Refer to the PXIe-5646 Specifications document for details about the minimum and maximum levels allowed by the PXIe-5646 REF IN front panel connector.

Note Note  The PXIe-5646 does not support multidevice synchronization with daisy-chained Reference Clocks, for example, REF OUT to REF IN.
Note Note  This topic applies only when programming the PXIe-5646 using NI-RFSA and NI-RFSG.

The PXIe-5646 supports synchronization using low-level properties and attributes instead of supporting NI-TClk synchronization. Use the following NI-RFSA and NI-RFSG properties and attributes to synchronize the PXIe-5646 with another PXIe-5646 or to synchronize the generator and analyzer on one PXIe-5646 module.

NI-RFSA Property NI-RFSA Attribute
Sync Sample Clock Master NIRFSA_ATTR_SYNC_SAMPLE_CLOCK_MASTER
Sync Sample Clock Dist Line NIRFSA_ATTR_SYNC_SAMPLE_CLOCK_DIST_LINE
Sync Start Trigger Master NIRFSA_ATTR_SYNC_START_TRIGGER_MASTER
Sync Start Trigger Dist Line NIRFSA_ATTR_SYNC_START_TRIGGER_DIST_LINE
Sync Ref Trigger Master NIRFSA_ATTR_SYNC_REF_TRIGGER_MASTER
Sync Ref Trigger Dist Line NIRFSA_ATTR_SYNC_REF_TRIGGER_DIST_LINE
Sync Ref Trigger Delay Enabled NIRFSA_ATTR_SYNC_REF_TRIGGER_DELAY_ENABLED
Sync Advance Trigger Master NIRFSA_ATTR_SYNC_ADVANCE_TRIGGER_MASTER
Sync Advance Trigger Dist Line NIRFSA_ATTR_SYNC_ADVANCE_TRIGGER_DIST_LINE

NI-RFSG Property NI-RFSG Attribute
Sync Sample Clock Master NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_MASTER
Sync Sample Clock Dist Line NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_DIST_LINE
Sync Script Trigger Master NIRFSG_ATTR_SYNC_SCRIPT_TRIGGER_MASTER
Sync Script Trigger Dist Line NIRFSG_ATTR_SYNC_SCRIPT_TRIGGER_DIST_LINE
Sync Start Trigger Master NIRFSG_ATTR_SYNC_START_TRIGGER_MASTER
Sync Start Trigger Dist Line NIRFSG_ATTR_SYNC_START_TRIGGER_DIST_LINE

For repeatable phase offsets between multiple RF channels, share the LO between channels. These channels could be RF IN or RF OUT channels on multiple devices or on a single device. For example, to synchronize two analyzers in NI-RFSA or two generators in NI-RFSG, complete the following steps:

  • NI-RFSA
    1. Set the LO Export Enabled property or NIRFSA_ATTR_LO_EXPORT_ENABLED attribute to TRUE for one analyzer.
    2. Set the LO Source property or NIRFSA_ATTR_LO_SOURCE attribute to LO_In on the other analyzer.
    3. Set the LO Frequency property or NIRFSA_ATTR_LO_FREQUENCY attribute to the frequency of the LO signal you are providing to the device.
  • NI-RFSG
    1. Set the LO Out Enabled property or NIRFSG_ATTR_LO_OUT_ENABLED attribute to TRUE for one generator.
    2. Set the LO Source property or NIRFSG_ATTR_LO_SOURCE attribute to LO_In on the other generator.
    3. Set the Upconverter Center Frequency (Hz) property or NIRFSG_ATTR_UPCONVERTER_CENTER_FREQUENCY attribute to the frequency of the LO signal you are providing to the device.

If your I/Q carrier frequency is below 375 MHz, you must provide an LO signal to the LO IN terminal that is twice your I/Q carrier frequency and write this value to the niRFSA LO Frequency property or the NIRFSA_ATTR_LO_FREQUENCY attribute.

Related Topics

NI-RFSA Properties

NI-RFSA C Function Reference

NI-RFSG Properties

NI-RFSG C Function Reference

Synchronizing Sample Clock and Sampled Reference Clock Signals—Refer to this topic for more information about synchronizing PXIe-5646 Sample Clock and Sampled Reference Clock signals.

FPGA Basecard Synchronization—Refer to this topic for more information about synchronizing the PXIe-5646 using the instrument design libraries.

Synchronization Frequency Range—Refer to this topic for more information about supported frequencies for synchronizing an PXIe-5646 generator and analyzer.

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