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You can precisely synchronize multiple PXIe-5646 devices using the Sampled Reference Clock and the PXI triggers.
|Note This topic applies only when programming the PXIe-5646 using the instrument design libraries.|
The Sampled Reference Clock is a synchronization signal that exists inside the FPGA when the device is configured to use a 10 MHz external Reference Clock (from either REF IN or PXI_CLK10). The Sampled Reference Clock is in the Data Clock domain and asserts for one cycle out of every twenty-five, corresponding to every other rising edge of the 10 MHz Reference Clock.
|Note The PXIe-5646 does not support synchronization using daisy-chained Reference Clocks, for example, REF OUT to REF IN. For multidevice synchronization, lock all devices to phase-aligned Reference Clocks.|
The PXIe-5646 allows for multidevice synchronization with Sample Clock-level alignment. To perform multidevice synchronization, you must lock all devices to phase-aligned Reference Clocks. One way to do this is to specify PXI_CLK10 as the Reference Clock source for all devices. If you want to supply an external Reference Clock, some chassis allow you to override the PXI_CLK10 using an external reference input terminal on the chassis.
Alternatively, you can split the external Reference Clock with a passive power-divider or active distribution amplifier and provide a phase-aligned version to each PXIe-5646 REF IN front panel connector. Refer to the PXIe-5646 Specifications document for details about the minimum and maximum levels allowed by the PXIe-5646 REF IN front panel connector.
The LabVIEW FPGA Trigger Synchronization instrument design library provides a mechanism for triggering the PXIe-5646 devices using the Sampled Reference Clock and the PXI trigger lines. This feature allows for accurate and repeatable synchronization of the baseband signals (nominally less than 1 nanosecond).
When you have locked all PXIe-5646 modules to phase-aligned Reference Clocks, the Sample Clocks on all devices are phase aligned. However, the Data Clock and Sampled Reference Clock signals on all devices are not yet synchronized. The PXIe-5646 modules must go through an additional step in order to properly synchronize their respective Data Clock and Sampled Reference Clock signals to each other. Refer to the Synchronizing Multiple NI 5646R Devices.html file in the Simple VSA/VSG sample project and the VST Streaming sample project for more information about synchronizing the PXIe-5646 Data Clock and Sampled Reference Clock signals using the instrument design libraries.
Synchronizing PXIe-5646 modules in multiple chassis is similar to synchronizing modules in a single chassis. The Reference Clock used by all devices across multiple chassis must be phase-aligned, which may require you to use a system timing device. In addition, you must also distribute the Sync Signal across multiple chassis to properly align the FPGA Data Clocks across all devices as well as distribute the Start Trigger to initiate acquisition and generation at the same time across all devices.
Advanced applications may require you to manually adjust the delay of each device to fine-tune synchronization. The Fractional Interpolator and Fractional Decimator DSP FPGA VIs have a delay input, which changes the delay of the I/Q data pair with very fine resolution. The delay of the I/Q data pair directly affects the delay of the RF signals at the front panel connectors.
Synchronization Frequency Range—Refer to this topic for information about supported frequencies for synchronizing an PXIe-5646 generator and analyzer.
Synchronization Using NI-RFSA and NI-RFSG—Refer to this topic for more information about synchronizing PXIe-5646 modules using NI-RFSA and NI-RFSG.
Trigger Synchronization Overview—Refer to this topic for information about synchronizing the PXIe-5646 Data Clock and Sampled Reference Clock signals using the instrument design libraries.