Customizing the DIO with LabVIEW FPGA

NI RF Vector Signal Transceivers Help

Edition Date: June 2018

Part Number: 373680F-01

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Because the DIO buffers are connected directly to the FPGA, you can use LabVIEW FPGA to program the functionality of the individual DIO signals for custom applications. Typical applications include interfacing with serial buses, such as SPI or I2C, high-speed I/Q data streaming, and custom DUT control.

For applications where very low-level control of the DIO is required, LabVIEW FPGA allows you to customize the DIO using VHDL inside a component-level IP (CLIP) interface. For example, the VHDL inside a CLIP can control the use of input/output block (IOB) flip-flops, single-data rate (SDR) or double-data rate (DDR) I/O, and the use of an MMCM on the CLK IN signal. The use of a CLIP with the DIO is mandatory, and the PXIe-5645 software includes a default CLIP that is sufficient for many applications. DDR interfaces are also supported with a custom IP integration node.

You must select a CLIP before using the DIO. Complete the following steps to select a CLIP:

  1. In the LabVIEW project, right-click DIO in the Project Explorer window, and select Properties from the shortcut menu to open the Properties dialog box.
  2. Select Enable DIO to enable the socketed CLIP. The Name box displays a list of compatible CLIPs. Select the CLIP you want to use. The Details box displays information about each CLIP.
  3. Some signals associated with the CLIP must be linked to the clock domain in which they are used in the LabVIEW FPGA block diagram. Choose the Clock Selections category and select the appropriate clock domain for each signal listed.
  4. The CLIP may also contain VHDL generics that you can customize. Select the Generics category to update the value of a generic.
    Note Note  By default, CLIP I/O has additional synchronization registers on inputs and outputs, which can influence your code on a clock cycle basis. NI does not recommend that you reduce the number of sync registers.


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