The FPGA target on the NI myRIO has a clock rate of 40 MHz, which means the clock cycle is 25 ns. To generate a frequency that is less than 40 MHz, you can change a signal on every x number of rising edges of the clock signal. The following figure shows an example of changing a 40 MHz clock signal on rising edges to generate 20 MHz and 10 MHz clock signals, respectively.
In the previous figure, you toggle the clock signal on every rising edge to generate the 20 MHz clock signal and toggle the clock signal on every other rising edge to generate the 10 MHz clock signal.
The frequency you want to generate on the NI myRIO must meet the following requirements:
You can use clock divisors to generate even lower frequencies for different I/O types. You can divide the base frequency by even numbers and use the generated clock to increment the counter. For example, with a clock divisor of 2, the lowest achievable frequency is 1/(50 ns * 65536) ≈ 305.17 Hz.
The following equation calculates frequencies that you can generate for pulse width modulation (PWM) I/O on the NI myRIO.
f_{PWM} = f_{clk} / (N * [X + 1])
where | f_{PWM} is the desired PWM frequency |
f_{clk} is the base clock frequency | |
N is the clock divisor | |
X is the number of counts before changing the signal |
The following equation calculates frequencies that you can generate for serial peripheral interface (SPI) I/O on the NI myRIO.
f_{SPI} = f_{clk} / (2 * N * [X + 1])
where | f_{SPI} is the desired SPI frequency |
f_{clk} is the base clock frequency | |
N is the clock divisor | |
X is the number of counts before changing the signal |
The PWM Express VI and SPI Express VI provide a Validate button that you can use to validate whether the Express VI can generate the frequency that you specify. If the specified frequency is not valid, both Express VIs coerce the specified value to the nearest valid value.