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SPI Express VI

LabVIEW 2013 for myRIO Module Help

Edition Date: June 2013

Part Number: 373925A-01

»View Product Info

Owning Palette: myRIO VIs

Requires: myRIO Module

Writes/reads data to/from a serial peripheral interface (SPI) slave device.

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
NameSpecifies the name of this Express VI. You can also double-click the name of this Express VI on the expandable node to edit the name.
ChannelSpecifies the SPI channel you want to use for writing/reading data to/from an SPI slave device.
ConnectionsSpecifies the NI myRIO pins that correspond to the SPI logic signals.
ModeSpecifies the mode of operation that this Express VI uses to communicate with the SPI slave device. Mode contains the following options:
  • Write—Specifies that this Express VI writes data to the SPI slave device.
  • Read—Specifies that this Express VI reads data from the SPI slave device.
  • Write/Read—Specifies that this VI writes and reads data to and from the SPI slave device at the same time.
FrequencySpecifies the frequency of the generated clock signal.
  • Frequency value—Specifies the value of the frequency. The default is 1.
  • Frequency unit—Specifies the unit of the frequency. The default is MHz.
  • Validate—Validates whether this Express VI can generate the frequency that you specify. If the specified frequency is not valid, this Express VI coerces the specified value to the nearest valid value.

    Related Information

    FPGA Clock Generation
Frame lengthSpecifies the number of bits that make up a single SPI transmission frame. The default is 8.
Advanced optionsSpecifies advanced configuration options for communicating with the SPI slave device.
  • Clock phase—Specifies the clock phase at which the data remains stable in the SPI transmission cycle. The default is Leading, which means the data is stable on the leading edge and the data changes on the trailing edge. Set Clock phase to Trailing if the data is stable on the trailing edge and the data changes on the leading edge.
  • Clock polarity—Specifies the base level of the clock signal and the logic level of the leading and trailing edges. The default is Low, which means the clock signal is low when idling, the leading edge is a rising edge, and the trailing edge is a falling edge. Set Clock polarity to High if the clock signal is high when idling, the leading edge is a falling edge, and the trailing edge is a right edge.
  • Data direction—Specifies the order in which the bits in the SPI frame are transmitted. The default is Most Significant Bit First, which specifies to send the most significant bit first and the least significant bit last. Set Data direction to Least Significant Bit First to send the least significant bit first and the most significant bit last.
View CodeDisplays the underlying code of this Express VI.

Block Diagram Inputs

ParameterDescription
Frames to WriteSpecifies the data that you want this Express VI to write to the SPI slave device. You can write multiple frames to the device at the same time. This input is available when you set Mode to Write or Write/Read.
Frame CountSpecifies the number of frames that you want this Express VI to read from the SPI slave device. This input is available only when you set Mode to Read.
error in (no error)Describes error conditions that occur before this node runs.

Block Diagram Outputs

ParameterDescription
Frames ReadReturns the data frames that this VI reads from the SPI channel. This output is available when you set Mode to Read or Write/Read.
error outContains error information. This output provides standard error out functionality.

 

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