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The FPGA target on the hardware has a clock rate of 40 MHz, which means the clock cycle is 25 ns. To generate a frequency that is less than 40 MHz, you can change a signal on every x number of rising edges of the clock signal. The following figure shows an example of changing a 40 MHz clock signal on rising edges to generate 20 MHz and 10 MHz clock signals, respectively.
In the previous figure, you toggle the clock signal on every rising edge to generate the 20 MHz clock signal and toggle the clock signal on every other rising edge to generate the 10 MHz clock signal.
The frequency to generate on the hardware must meet the following requirements:
You can use clock divisors to generate even lower frequencies for different I/O types. You can divide the base frequency by even numbers and use the generated clock to increment the counter. For example, with a clock divisor of 2, the lowest achievable frequency is 1/(50 ns * 65536) ≈ 305.17 Hz.
The following equation calculates frequencies that you can generate for pulse width modulation (PWM) I/O.
f _{PWM} = f _{clk} / (N * [X + 1])
where | f_{PWM} is the desired PWM frequency |
f_{clk} is the base clock frequency | |
N is the clock divisor | |
X is the number of counts before changing the signal |
The following equation calculates frequencies that you can generate for serial peripheral interface (SPI) I/O.
f _{SPI} = f _{clk} / (2 * N * [X + 1])
where | f_{SPI} is the desired SPI frequency |
f_{clk} is the base clock frequency | |
N is the clock divisor | |
X is the number of counts before changing the signal |
Some Express VIs include a Validate button for validating whether these Express VIs can generate the frequency that you specify. If you specify an invalid value for Frequency, the Express VIs coerce the specified value to the nearest valid value when you click the Validate button.
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