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The NI 5624R includes 12 general purpose digital lines. You can connect to these resources through the DIGITAL I/O port using a supported cable and accessory, such as the NI SHH19-H19-AUX (NI part number 152629-01 or 152629-02). These signals are 3.3 V LVCMOS bidirectional digital signals and may be used in a variety of applications. Direction is controlled independently for each channel through the LabVIEW FPGA I/O Method Node.
The DIGITAL I/O signals are connected to the FPGA through 3.3 V LVTTL buffers. These buffers allow for direction control, and isolation to protect the FPGA from overvoltage conditions. For exact I/O levels and input and output impedances, refer to the device specifications.
The digital lines are protected against overvoltage conditions. The device provides this protection through a combination of diode clamps to the +3.3 V and GND lines and a positive temperature coefficient resistor for impedance matching.
|Note The interface from the DIGITAL I/O LVTTL buffer to and from the FPGA is bidirectional. In the previous figure, DIR N represents the line direction. To guarantee that this line is not double-driven by both the FPGA and the buffer at the same time, the FPGA implements a direction control latency. This latency is a fixed delay between enabling the FPGA I/O buffer and setting the direction of the DIGITAL I/O. For more information on direction control latency, refer to the device specifications.|