FPGA I/O Resources

NI IF Digitizers 14.0 Help

Edition Date: September 2014

Part Number: 374716A-01

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You can use LabVIEW FPGA to program the FPGA on IF digitizers. Use FPGA I/O nodes to connect to the device I/O. You can configure FPGA I/O nodes for reading or writing. The FPGA I/O nodes connect to the front panel I/O, backplane I/O, and internal status signals of the module. The following tables describe LabVIEW FPGA I/O resources visible in the LabVIEW project.

Sample Data In

Name Description Data Type Access Method Required Clock Domain
IF In 0 Contains raw data from the ADC. The data is presented as 16 samples per cycle at 125 MHz loop rate. The oldest sample will be data [0]. Fixed-point Numeric <±, 12, 1>1 array, fixed-size 16. Each sample has an overflow bit that indicates if the sample exceeded the ADC range. If the sample exceeds the ADC range, the data value will be +/- full scale, either +2,047 or -2,048. Read Data Clock
IF In 0 Valid For each array of 16 data samples, this signal returns TRUE if the samples are valid and FALSE if the samples are not valid. This signal asserts after the ADC-FPGA link has initialized and remains TRUE as long as the Data Clock, which is derived from the ADC Clock, maintains the expected frequency. Boolean Read Data Clock
IF In 0 Overvoltage Error This signal returns TRUE while an overvoltage condition is present, and it returns FALSE when no overvoltage condition is present. The I/O signal is not latched; you can latch it on the FPGA diagram, if needed. After the I/O signal asserts, the device disconnects the IF In signal from the ADC to protect circuitry, and the Read Input Power Protection Status VI returns input power protection activated. These conditions persist until you call the Clear Input Power Protection VI on the host, or redownload or reset the FPGA. Boolean Read Any
1 The <±, 12, 1> notation corresponds to a signed, fixed-point number with a 12-bit word length and a 1-bit integer word length.

PFI and Digital I/O

Name Description Data Type Access Method Required Clock Domain
PFI 0 Controls PFI 0. This signal is connected to the PFI 0 front panel connector of the module. Boolean Read, Write, Set Output Data method, Set Output Enable method Any
DIO N Controls Digital I/O line N, where N is a DIO line number from 0 to 11. This signal is connected to the Digital I/O front panel connector of the module. Boolean Read, Write, Set Output Data method, Set Output Enable method Any

PXI

Name Description Data Type Access Method Required Clock Domain
PXI_Trig N Controls PXI trigger line N, where N is a PXI trigger line number from 0 to 7. For proper device and PXI system functionality when using PXI triggers with the LabVIEW FPGA Module, follow the guidelines in PXI Triggers. Boolean Read, Write, Set Output Data method, Set Output Enable method, Wait methods Any
PXI_Star Provides access to the PXI Star trigger line. Boolean Read, Wait methods Any
PXIe_Sync100 This signal becomes TRUE one PXIe_CLK100 cycle before each rising edge of PXI_CLK10. You can sample PXIe_Sync100 and use it as an enable signal to mirror the behavior of PXI_CLK10. Boolean Read, Wait methods PXIe_Clk100

Device Status

Name Description Data Type Access Method Required Clock Domain
Active LED Controls the Active LED on the front panel of the module. You can set the LED to Off, Green, Red, or Amber. Enumerated Type Read, Write Any
DRAM Ready Indicates that DRAM has completed initialization and is ready to be accessed. This signal is FALSE when the FPGA first starts running. Boolean Read Any

Front End and ADC Test Signals

Name Description Data Type Access Method Required Clock Domain
Measure ADC Pulse Output signal that measures the ADC pipeline delay. Reserved for NI use. Use this I/O method only with IP provided by NI. Boolean Write Data Clock
Measure Synchronization Pulse Output signal that measures the synchronization skew between modules. Use this I/O method only with IP provided by NI. Boolean Write PXIe_CLK100

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