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Edition Date: February 2017

Part Number: 375482B-01

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Tutorial: Creating and Exporting a PLD Schematic

This tutorial demonstrates how to create and simulate a PLD schematic.

To complete this tutorial, you will need:

  • The NI Digital Electronics FPGA Board and its driver.
  • A supported version of Xilinx ISE.
  • When you install Xilinx, select the Get Free ISE WebPack License option.

The process described here can also be used to target any of these Digilent boards:

  • Basys FPGA Board.
  • Basys 2 FPGA Board.
  • Nexys 2 FPGA Board.
  • Nexys 3 FPGA Board.
  • Nexys 4 FPGA Board.
  • NI Digital Systems Development Board.

You will create the following simple 4-bit parity generator:

When complete, PLD1 will contain the following logic:

  The completed design is found at ...\samples\PLD Sample Circuits\ParityGenerator.

You will then export the PLD device to the National Instruments Digital Electronics FPGA Board, which includes the Xilinx Spartan 3E FPGA.

Creating the design

Complete the following steps:

  1. Select File»New.
  2. The New Design dialog box displays.

  3. Select Blank and click Create.
  4. A blank Multisim design file displays.

  5. Place VCC, J1 and the probes.
  6. VCC is in the Sources group, POWER_SOURCES family.

    J1 is DSWPK_4, found in the Basic group, SWITCH family.

    The probes (PROBE_GREEN) are in the Indicators group, PROBE family.

  7. Change the Reference Designators for the probes to ODD and EVEN.
  8. Save the design file as ParityGenerator.
  9. Select Place»New PLD subcircuit.
  10. The New PLD Design dialog box displays with NI Digital Electronics FPGA Board preselected.

  11. Click Next.
  12. Enter Parity Generator in the PLD subcircuit name field and click Next.
  13. Click Uncheck all and then select LED0, LED1, SW0, SW1, SW2 and SW3.
  14. Click Finish.
  15. Click on the workspace to place the Parity Generator subcircuit:


  16. Wire the components as shown below:


  17. Double-click on PLD1 and click Open subsheet.
  18. The contents of the subcircuit display, with the port connectors LED0, LED1, SW0, SW1, SW2 and SW3.

  19. Click in the PLD components toolbar to display the Select a Component (PLD Mode) dialog box and select and place an XOR2 gate. .
  20. Repeat until you have placed a total of three XOR2 gates.
  21. Click in the PLD components toolbar to display the Select a Component (PLD Mode) dialog box and select and place an inverter. .
  22. Arrange the components as shown below:


  23. Wire the PLD subcircuit as shown below:


  24. Save the PLD subcircuit.
  25. Return to the main design page and save the design.

This topic refers to education-specific features of Multisim.

Simulating the design

Complete the following steps to simulate your design.

  1. Start simulation and use J1 to specify 4-bit words.
  2. The circuit counts the number of HIGH inputs in the word and displays the result on the probes, one for an ODD number of HIGH inputs and one for an EVEN number of HIGH inputs.

    4-Bit Parity Generator Truth Table:



  3. Stop the simulation.

This topic refers to education-specific features of Multisim.

Exporting the design

Complete the following steps to export your design to the NI Digital Electronics FPGA Board.

  1. Connect the NI Digital Electronics FPGA Board to your computer and switch it on.
  2. Open the PLD subcircuit in Multisim so that it is the active page.
  3. Select Transfer»Export to PLD.
  4.   This command is disabled if the active page is not a PLD design.

    The PLD Export dialog box displays.

  5. Select Program the connected PLD.
  6. Click Next.
  7. Step 2 of the PLD Export dialog box displays.

  8. Under Xilinx tool, select the 64-bit version of your installed Xilinx tool, for example, Xilinx ISE Design Suite 14.5.
  9. If it is not in the list, manually select the directory it is installed in.

  10. Click Refresh to check the connection.
  11. The Device Status dialog box displays. After a few seconds, the Device status changes to Detected.

      If the Device status changes to Not connected or drivers not installed, confirm that the 64-bit version of a supported Xilinx tool is selected, the FPGA board is connected and switched on and you have up-to-date drivers for the board. Click Refresh.

  12. Click Finish.
  13. A PLD Export dialog box displays the status of the steps involved in the process. For example, Step 7 of 11: Map.

    More detailed messages, warnings, and any errors appear in the Results tab as the selected Xilinx tool programs the connected PLD. These messages are supplied from the Xilinx tool. For information about these, refer to the Xilinx help.

    At the same time, an indicator consisting of moving zeros and ones appears below the hardware device target icon in the Design Toolbox.

    If you cancel the PLD export, this indicator continues to move until the current step is fully terminated.

    If you click Hide, the PLD Export dialog box disappears, but the indicator continues to move until the export completes. To show the PLD Export dialog box again, select Transfer»View export progress.

  14. When the export is completed:
    • Toggle switches SW0 - SW3 on the Digital Electronics FPGA Board and compare the results to the 4-Bit Parity Generator Truth Table in step 1.

This topic refers to education-specific features of Multisim.


 

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