Understanding Latency (ELVIS RIO Control Toolkit)

LabVIEW 2016 ELVIS RIO Control Toolkit Help

Edition Date: June 2016

Part Number: 376300A-01

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Latency refers to the time it takes to complete an operation. When you use the NI ELVIS RIO CM Express VIs to acquire or generate signals, latency has different meanings.

Latency in Signal Acquisition

Latency in signal acquisition refers to the time that the NI ELVIS RIO CM needs to transfer the acquired signal to the real-time processor. In the n samples mode, latency involves the software or memory transfer that gets the signal into the correct memory and delivers the signal to the algorithm.

When you use the NI ELVIS RIO CM Express VIs to perform signal acquisition in the n samples, latency refers to the time it takes to complete the following processes:

  • DMA read operation—FPGA transfers the signal values from the FPGA buffer to the real-time buffer. DMA is a FIFO-based method of transferring data between an FPGA target and the host.
  • Data copying—The real-time processor copies the signal values from the real-time buffer to the algorithm.
Note  The latency changes when the number of samples you want to read changes. For example, if there is more data to read, data copying takes more time.

Latency in Signal Generation

Latency in signal generation refers to the time that the NI ELVIS RIO CM needs to export the acquired signal to another data acquisition (DAQ) device. In the n samples mode, latency involves the software or memory transfer that gets the signal from the algorithm and delivers the signal into the correct memory.

When you use the NI ELVIS RIO CM Express VIs to perform signal generation in the n samples mode, the following processes can result in latency. The actual latency varies depending on whether you place a checkmark in the Wait until done? checkbox on these Express VIs.

  • Data copying—The real-time processor copies the signal values from the algorithm to the real-time buffer.
  • DMA write operation—The real-time processor transfers the signal values from the real-time buffer to the FPGA side.
  • Interrupt processing—When the FPGA buffer finishes writing n sample values to the pins on the NI ELVIS RIO CM, FPGA sends an interrupt to the real-time processor. When the real-time processor receives the interrupt, the real-time processor continues to write another n sample values to the FPGA buffer.

The following figure shows the latency in signal generation when you place a checkmark in the Wait until done? checkbox. Latency refers to the time it takes to complete the data copying, DMA write operation, and interrupt processing.

The following figures show the latency in signal generation when the Wait until done? checkbox does not contain a checkmark. In this situation, RT continuously writes signal values from the algorithm to the real-time buffer. Meanwhile, RT uses another loop to transfer the values from the real-time buffer to the FPGA buffer. Thus, latency refers to the time it takes to complete the DMA write operation and interrupt processing. Typically, this latency is 400 µs.

Related Information

Analog Input Express VI

Analog Output Express VI

Digital Input Express VI

Digital Output Express VI

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