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NI ATCA FPGA Modules includes a Socketed CLIP interface for using both DACs simultaneously with the same external sampling clock. The primary DAC (signal AO 0) must always be used in a LabVIEW design, and must be driven by a stable external sampling clock at all times. The secondary DAC (signal AO 1) is optional. It may be left out of a design, and its external clock input can be left disconnected when not in use. The logic clock generated by the CLIP for the diagram is derived purely from the output of the primary DAC (AO 0).
For each DAC, 8 samples are provided in the user diagram per data clock cycle. Therefore, the data clock always runs at 1/8th the frequency of the sampling clock. For example, at a sampling clock rate of 2.5 GHz, the data clock will run at 312.5 MHz.
Due to the complexity of the internal logic in the Socketed CLIP, and to provide more flexibility for cases when the external sampling clock is connected at runtime, a “CLIP Reset” signal is provided for explicit control over the reset behavior of the CLIP in the diagram.
|Note The self-calibration algorithm between the CLIP and DAC takes approximately 1 minute to complete.|
To help manage this initialization time, a “CLIP Ready” signal is also provided which can be monitored to determine when the DAC is ready to accept output data. Any interruptions to the external clock or software events, such as resetting the diagram or downloading a new bitstream, should always be followed by a reset to the CLIP.