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AIO-3691 Socketed CLIP Interface

NI ATCA FPGA Modules Help

Edition Date: March 2017

Part Number: 376468A-01

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NI ATCA FPGA Modules includes a Socketed CLIP example for the AIO-3691, which features an optimally hardware-efficient implementation of the Aurora protocol across all lanes running at 10.4167 GHz.

Each SFF-8644 port has its own x4 Aurora IP instance and data ports to the LabVIEW diagram, but all four ports share a single user clock.

Note

Note  Sharing a clock conserves a significant number of resources on the FPGA and prevents unnecessary clock domain crossing logic from being inferred, since all IP instances share the same external reference clock and do not require any additional buffering.

Note Note  Since all four ports share a single user clock sourced by a single Aurora instance, Port 0 must always be connected to use this CLIP. Even if other ports are not in use, a stable link on Port 0 is required to maintain a valid user clock.

AIO-3691 Aurora CLIP Contents

aio3691_aurora_clip_contents

AIO-3691 Aurora CLIP Signals

Port Direction Clock Domain Description
fmc_dp_c2m_p(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
fmc_dp_c2m_n(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
fmc_dp_m2c_p(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
fmc_dp_m2c_n(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
fmc_gtbclk0_m2c_p In (pad) N/A Reference clock input pins from the FMC connector. These ports are directly connected to the top-level ports of the FPGA and are unbuffered. Therefore, IBUFDS_GTE2 instances are required in the CLIP.
fmc_gtbclk0_m2c_n In (pad) N/A Reference clock input pins from the FMC connector. These ports are directly connected to the top-level ports of the FPGA and are unbuffered. Therefore, IBUFDS_GTE2 instances are required in the CLIP.
fmc_gtbclk1_m2c_p In (pad) N/A Reference clock input pins from the FMC connector. These ports are directly connected to the top-level ports of the FPGA and are unbuffered. Therefore, IBUFDS_GTE2 instances are required in the CLIP.
fmc_gtbclk1_m2c_n In (pad) N/A Reference clock input pins from the FMC connector. These ports are directly connected to the top-level ports of the FPGA and are unbuffered. Therefore, IBUFDS_GTE2 instances are required in the CLIP.
fmc_312p5_refclk(3:0) In N/A Reference clock inputs for the shared 312.5 MHz oscillator. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
fmc_jc_refclk(3:0) In N/A Reference clock inputs for the GTH reference clock generated by the jitter cleaner. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
fmc_sma_refclk(3:0) In N/A Reference clock inputs for the shared front panel SMA connector. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
fmc_fpga_ready In Async Signal driven by fixed logic to indicate that all clocks and power supplies required by the FPGA are active and stable.
fmc_jc_srcclk Out N/A Optional output signal which can be driven out from the CLIP to be used as the source clock for the jitter cleaner (useful for recovered-clock applications where the interface IP produces a clock that must be externally filtered for reuse as a reference clock). The source clock to be driven out to the jitter cleaner is selected via the External Clock Configuration properties window.

 

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