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Each FPGA has a designated TI LMK04808 jitter-cleaning dual-PLL device, which is used when an ultra-low phase noise clock must be generated from a clock source inside the FPGA.
The primary input to the jitter cleaner is driven by a differential pair on the FPGA. The jitter cleaner then outputs two different clocks back to the FPGA: one MGT reference clock, which is duplicated so that it can reach every MGT quad on the FPGA, and one SMA output clock.
The architecture of the LMK04808 uses a voltage-controlled crystal oscillator (VCXO) to drive the first-stage PLL. This VCXO is 122.88 MHz1.
|Note When choosing which output frequencies to generate, consider the VCXO frequency because it impacts the set of valid frequencies available for the internal voltage-controlled oscillator (VCO) and output clocks of the LMK04808.|
For more information on the configuration and performance of the jitter cleaner, refer to the LMK04808 datasheet at www.ti.com.
Software features are provided to fully configure the jitter cleaner based on a user-defined set of input and output frequencies.
1This frequency was chosen to meet the requirements of many wireless telecommunications applications.