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The ATCA-3671 hardware has 76 user-accessible MGTs available to the user for high-speed, low-latency data communication between devices.

The FPGAs on the ATCA-3671 feature a Xilinx GTH transceiver, which allows for supported line rates up to 12.5 Gbps on most interfaces.

The ATCA-3671 user-accessible MGTs are organized into five different groups:

• Three MGT groups connect the four FPGAs in a full mesh pattern
• One MGT group connects the FPGAs to the ATCA I/O (AIO) slot
• One MGT group connects the FPGAs to the Rear Transition Module (RTM) slot

 

The following figure shows the logical structure of the five transceiver groups.

1  AIO	3  FPGA Ring Up	5  FPGA Diagonal
2  RTM	4  FPGA Ring Down

Each transceiver group is defined in the following table.

Name	Number of MGTs	Connection	Configuration
AIO	16	Each FPGA to a designated AIO module connector	Depends on which AIO module is populated in each slot
RTM	16	Each FPGA to the RTM	Depends on which RTM is populated in the system
FPGA Ring Up	16	Upstream, between FPGAs	Ring (A to D, B to A, C to B, and D to C)
FPGA Ring Down	16	Downstream, between FPGAs	Ring (A to B, B to C, C to D, and D to A)
FPGA Diagonal	12	Diagonal, between FPGAs	Diagonal (A to C, B to D, C to A, D to B)