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The ATCA-3671 family of devices provides a wide range of options for delivering reference clocks to each of the MGT interfaces in the system.
Three MGT reference clocks are distributed to reach every MGT bank (Quad) in every FPGA on the ATCA-3671, as shown in the following table.
|MGT Reference Clock||Description|
|Fixed oscillator||A pair of fixed 312.5 MHz oscillators are used on the ATCA-3671 to deliver this common reference clock frequency to the entire board. One oscillator drives all reference clocks on FPGAs A and B, and the other drives all reference clocks on FPGAs C and D.|
|External SMA||An SMA connector on the front panel may be used to distribute an external reference clock to every transceiver on the entire board.|
|Jitter cleaner||Each FPGA has its own jitter-attenuating, dual-PLL device (LMK04808) that is capable of creating an ultra-low phase noise output that can be used as an MGT reference clock to all transceivers on the same FPGA.|
Additional reference clock options are available on the AIO and RTM interfaces.