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Configuring a New ATCA-3671 FPGA Target

NI ATCA FPGA Modules Help

Edition Date: March 2017

Part Number: 376468A-01

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After creating a new FPGA target for the ATCA-3671, some configuration is required before you can compile FPGA VIs for the ATCA-3671.

Adding and Assigning CLIP Files

The ATCA-3671 requires a CLIP to be assigned to each socket and will not compile if that requirement is not met. Complete the following steps to assign a CLIP file to each socket.

  1. Right-click the FPGA target and select Properties from the shortcut menu to display the FPGA Target Properties dialog box.
  2. Select Component-Level IP from the Category list to display the Component-Level IP Properties page.
  3. Select Add.
  4. Select all the CLIP XML files that you need for your design. These files are your CLIP declaration files.
    Note

    Note  The default CLIP files are installed in the LabVIEW folder at Targets\NI\FPGA\ATCA\CLIP. If you are not using a specific socket in your design, add the corresponding Idle MGT CLIP XML file located in the Idle subdirectory.

  5. Click OK.
  6. Right-click a socket on the FPGA target and select Properties from the shortcut menu to display the Component-Level IP Properties dialog box.
  7. Select the corresponding CLIP declaration that you added in step 4 from the Socketed Component-Level IP Declaration pull-down menu.
  8. Click OK. The Project Explorer window includes the I/O defined in the declaration XML file.
  9. Repeat steps 6 through 8 for each socket on the target.

Configuring the Clock Routing on the FPGA

To use the jitter cleaner or FPGA In/Out SMA clock for your design, you must configure the clock routing before compiling FPGA VIs for the ATCA-3671. Complete these steps before attempting to compile a bitfile for the ATCA-3671 to avoid the following error:

Code Description
-680700 You must review the Clocking and IO Preference Page Settings on the External Clock Configuration CLIP Socket.

Complete the following steps to configure the clock routing on the FPGA.

  1. Right-click the External Clock Configuration item in the target and select Properties from the shortcut menu to display the External Clock Properties dialog box.
  2. Select the appropriate values for your design and use according to the following table. You can choose to leave all settings at the default values.
    Design Use Action
    Jitter cleaner In use Select the clock source and output frequencies.
    Not in use Leave the settings at the default values.
    FPGA In/Out SMA Using as output Select the Enable FPGA In/Out SMA clock as output checkbox and select a clock source from the FPGA In/Out SMA Clock Source pull-down menu.
    Using as input Leave the settings at the default values.
    Not in use Leave the settings at the default values.
  3. Click OK.

 

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