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After creating a new FPGA target for the ATCA-3671, some configuration is required before you can compile FPGA VIs for the ATCA-3671.
The ATCA-3671 requires a CLIP to be assigned to each socket and will not compile if that requirement is not met. Complete the following steps to assign a CLIP file to each socket.
Note The default CLIP files are installed in the LabVIEW folder at Targets\NI\FPGA\ATCA\CLIP. If you are not using a specific socket in your design, add the corresponding Idle MGT CLIP XML file located in the Idle subdirectory.
To use the jitter cleaner or FPGA In/Out SMA clock for your design, you must configure the clock routing before compiling FPGA VIs for the ATCA-3671. Complete these steps before attempting to compile a bitfile for the ATCA-3671 to avoid the following error:
|-680700||You must review the Clocking and IO Preference Page Settings on the External Clock Configuration CLIP Socket.|
Complete the following steps to configure the clock routing on the FPGA.
|Jitter cleaner||In use||Select the clock source and output frequencies.|
|Not in use||Leave the settings at the default values.||FPGA In/Out SMA||Using as output||Select the Enable FPGA In/Out SMA clock as output checkbox and select a clock source from the FPGA In/Out SMA Clock Source pull-down menu.|
|Using as input||Leave the settings at the default values.|
|Not in use||Leave the settings at the default values.|