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RTM-3661 Socketed CLIP Interface

NI ATCA FPGA Modules Help

Edition Date: March 2017

Part Number: 376468A-01

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NI ATCA FPGA Modules includes a Socketed CLIP example for the RTM-3661.

Note Note  The x8 PCI Express host interface is critical to operation of the ATCA-3671 FPGA module in LabVIEW and is contained in the fixed logic of the FPGA. Therefore, those MGT lanes are not included in the Socketed CLIP definition. Only the eight total lanes of QSFP port connectivity are user-accessible.

The provided example features an optimally hardware-efficient implementation of the Aurora protocol across all lanes running at 10.3125 GHz. Each QSFP port has its own x4 Aurora IP instance and data ports to the LabVIEW diagram, but both ports share a single user clock.

Note Note  Sharing a clock conserves a significant number of resources on the FPGA and prevents unnecessary clock domain crossing logic from being inferred, since all IP instances share the same external reference clock and do not require any additional buffering.

RTM-3661 Aurora CLIP Contents

rtm_aurora_clip_contents

RTM-3661 Aurora CLIP Signals

Port Direction Clock Domain Description
rtm_txp(7:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
rtm_txn(7:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
rtm_rxp(7:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
rtm_rxn(7:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
rtm_312p5_refclk(1:0) In N/A Reference clock inputs for the shared 312.5 MHz oscillator. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
rtm_jc_refclk(1:0) In N/A Reference clock inputs for the GTH reference clock generated by the jitter cleaner. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
rtm_sma_refclk(1:0) In N/A Reference clock inputs for the shared front panel SMA connector. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
rtm_jc_srcclk Out N/A Optional output signal which can be driven out from the CLIP to be used as the source clock for the jitter cleaner (useful for recovered-clock applications where the interface IP produces a clock that must be externally filtered for reuse as a reference clock). The source clock to be driven out to the jitter cleaner is selected via the External Clock Configuration properties window.
rtm_fpga_ready In Async Signal driven by fixed logic to indicate that all clocks and power supplies required by the FPGA are active and stable.

 

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