3681 Gain Config VI

NI-ATCA FPGA Modules Help

Edition Date: September 2018

Part Number: 376468B-01

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Reads/writes the gain range configuration setting of an attached AIO-3681 module. This VI should be placed within an SCTL at or below 250 MHz. Accessing this setting requires multiple executions of the VI. Use hand shaking for valid execution. Only use one AIO Config VI per FPGA. To access additional ADC configuration options, such as mode configuration and calibration, use the 3681 Generic Config VI.

3681 gain config diagram

abc gain range (register value) specifies the gain range setting to save to the AIO-3681 module. Use the 3681 Encode Gain Selection VI in order to convert a mV range to the appropriate register value.
FPGA_ID channel specifies which input channel(s) to read/write the gain setting of.
FPGA_ID input valid allows you to specify TRUE to start a new gain setting read/write transaction. A new read/write only occurs if this parameter is set to TRUE when ready for input was TRUE the previous cycle.
FPGA_ID write (T) specifies whether the register value is modified. If TRUE, gain range (register value) is written to the AIO-3681 gain range setting. If FALSE, the existing register value is read.
FPGA_ID actual gain range (register value) indicates the actual gain range setting of the AIO-3681 module. Index 0 and 1 correspond to channels I and Q, respectively. Channels not specified for configuration report a value of 0. Use the 3681 Decode Gain Selection VI to convert the register values to the corresponding gain range in mV.
FPGA_ID output valid indicates whether the last requested gain configuration has completed and whether the values of actual gain range (register value) are valid.
FPGA_ID ready for input indicates when the VI is in an idle state and ready to perform a new gain configuration read/write.


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