AIO-3681 Digitizer Module for FMC

NI-ATCA FPGA Modules Help

Edition Date: September 2018

Part Number: 376468B-01

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This section includes reference information about the AIO-3681 module, including the block diagram and socketed CLIP interface.

The AIO-3681 is an expansion module that provides single- or dual-channel 12-bit analog-to-digital conversion at RF sampling rates up to 4 GS/s, depending on hardware configuration.

It features a TI ADC12D2000RF analog-to-digital converter (ADC) component and is shipped with software support for both dual-channel and interleaved dual-edge sampling (single-channel) modes of operation.


Note   For the ADC, 8 samples per channel are provided in the user diagram per data clock cycle. Therefore, the data clock always runs at one-eighth the frequency of the sampling clock. For example, at a sampling clock rate of 2.5 GHz, the data clock will run at 312.5 MHz.

Due to the complexity of the internal logic in the Socketed CLIP, and to provide more flexibility for cases when the external sampling clock is connected at runtime, a CLIP Reset signal is provided for explicit control over the reset behavior of the CLIP in the diagram.


Note   The self-calibration algorithm between the CLIP and ADC takes approximately 20 seconds to complete.

To help manage this initialization time, a CLIP Ready signal is also provided which can be monitored to determine when the ADC is ready to accept input data. Any interruptions to the external clock or software events, such as resetting the diagram or downloading a new bitstream, should always be followed by a reset to the CLIP.


Note   Rerun calibration after significantly altering the settings or conditions of the AIO-3681. To preform calibration, use the 3681 Generic Config VI to set the CAL bit (Addr: 0h; Bit 15) to low for a minimum of 1,280 sample clock cycles and then high for a minimum of 1,280 sample clock cycles. Visit and enter the Info Code exsq59 to access the specifications for the ADC12D2000RF and navigate to section 17.3.3 of the document for more information about the calibration feature.

If the CLIP Calibration Status signal is true, AIO-3681 CLIP Calibration was successful. If CLIP Calibration Status signal is false after CLIP Initialization or Reset, calibration was unsuccessful and you should re-download the FPGA bitstream.


Note   You can change gain range and configuration registers using 3681 Gain Config and 3681 Generic Config.

Single-Channel AIO-3681 Port Diagram

AIO-3681 single-channel

Dual-Channel AIO-3681 Port Diagram

AIO-3681 dual-channel


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