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There are several ways to configure the onboard and external clocks on the ATCA-3671.
The clocking resources available on the system are summarized in the table below. If the software programming environment provides support for runtime configuration of clocking resources, refer to specific software product documentation, such as the LabVIEW Help, for more information.
The following table describes the ATCA-3671 clock sources.
|Fixed 100 MHz||N/A||A single 100 Fixed MHz reference clock is distributed to all four FPGAs on the ATCA-3671. This clock is free-running and may be used to derive any other clock frequencies desired inside the FPGA.|
|DDR3 Clock||N/A||A single 400 Hz reference clock is distributed to all four FPGAs on the ATCA-3671 for explicit use by the soft double data rate type three (DDR3) memory controller logic in the FPGA. The actual frequency of the logic clock available on the user interface side of the memory controller may vary based on the software platform, but is typically 167 MHz for the maximum DDR3 dynamic random access memory (DRAM) speed of 1,333 MHz.|
|SYNC ASYNC B||Input||Each of these two independent signals can be used to drive a clock to all four FPGAs on the ATCA-3671. By default, the SMA input on the front panel of the system is enabled as the signal source. However, in environments where a full ATCA backplane is present, this setting can be overridden in firmware to select the corresponding ATCA backplane signals to use the source instead. When added to a LabVIEW project, these clock sources are defined as free-running base clocks which support derived clocks. Therefore, the external clock source must be connected and stable at the correct frequency before running the FPGA application, even if they are not explicitly used in the diagram. Otherwise, errors are reported. In addition, the SYNC A and SYNC B signals must not be used as clocks in the same application (and vice versa) if they are used as FPGA I/O.|
|CLK IN/OUT ACLK IN/OUT BCLK IN/OUT CCLK IN/OUT D||Input/output||Each of these connectors on the front panel are coupled to one FPGA on the ATCA-3671 (denoted by A, B, C, or D) as either an input or output. The direction of the signal is configured in software, and can be changed dynamically at runtime. In LabVIEW, this clock source for each FPGA is defined as an external clock. This implies that it may not always be stable or connected and therefore cannot be used as the default top level clock or to generate derived clocks.|
|JC OUT AJC OUT BJC OUT CJC OUT D||Output||Each FPGA on the ATCA-3671 can drive out an ultra-low phase noise clock through a designated onboard jitter cleaning phase-locked loop (PLL). The exact frequency configuration of this PLL is controlled by software. See Configuring the Jitter Cleaner for Use as a Clock Source for more information.|
|MGT REF||Input||An input on the front panel used to distribute a single multi-gigabit transceiver (MGT) reference clock to every user-accessible high-speed transceiver on all four FPGAs on the ATCA-3671.|
|AIO CLK||Input||An input on the front panel used to drive an auxiliary external clock into all four of the AIO slots on the front panel of the ATCA-3671. This clock is not driven directly into the FPGA. Therefore, its usage and availability are dependent on the ATCA I/O module present in the system.|