Inter-FPGA Socketed CLIP Interfaces

NI-ATCA FPGA Modules Help

Edition Date: September 2018

Part Number: 376468B-01

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NI ATCA FPGA Modules includes Socketed CLIP examples for the inter-FPGA MGT groups.

The ATCA-3671 - Aurora Pattern example project includes an optimally hardware-efficient implementation of the Aurora protocol across all inter-FPGA lanes running at 12.5 Gbps. For the Ring Up and Ring Down groups, the CLIP consists of four x4 Aurora IP instances. For the Diagonal group, the CLIP consists of three x4 Aurora IP instances. Data is presented to the LabVIEW diagram in the same format as the Aurora IP structure, but each MGT group shares a single user clock between all instances.

note Note  Sharing a clock conserves a significant number of resources on the FPGA and prevents unnecessary clock domain crossing logic from being inferred, since all IP instances share the same external reference clock and do not require any additional buffering.

FPGA Diagonal Aurora CLIP Contents

fpga_diagonal_aurora_clip_contents

FPGA Diagonal Aurora CLIP Signals

Port Direction Clock Domain Description
diag_txp(14:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
diag_txn(14:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
diag_rxp(14:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
diag_rxn(14:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
diag_312p5_refclk(3:0) In N/A Reference clock inputs for the shared 312.5 MHz oscillator. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
diag_jc_refclk(3:0) In N/A Reference clock inputs for the GTH reference clock generated by the jitter cleaner. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
diag_sma_refclk(3:0) In N/A Reference clock inputs for the shared front panel SMA connector. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
diag_fpga_ready In Async Signal driven by fixed logic to indicate that all clocks and power supplies required by the FPGA are active and stable.

FPGA Ring Down and Ring Up CLIP Contents

fpga_ring_down_and_ring_up_clip_contents

FPGA Ring Up Aurora CLIP Signals

Port Direction Clock Domain Description
ring_up_txp(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
ring_up_txn(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
ring_up_rxp(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
ring_up_rxn(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
ring_up_312p5_refclk(3:0) In N/A Reference clock inputs for the shared 312.5 MHz oscillator. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_up_jc_refclk(3:0) In N/A Reference clock inputs for the GTH reference clock generated by the jitter cleaner. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_up_sma_refclk(3:0) In N/A Reference clock inputs for the shared front panel SMA connector. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_up_fpga_ready In Async Signal driven by fixed logic to indicate that all clocks and power supplies required by the FPGA are active and stable.

FPGA Ring Down Aurora CLIP Signals

Port Direction Clock Domain Description
ring_down_txp(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
ring_down_txn(15:0) Out (pad) N/A Dedicated high-speed serial transmit pins for GTH transceivers.
ring_down_rxp(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
ring_down_rxn(15:0) In (pad) N/A Dedicated high-speed serial receive pins for GTH transceivers.
ring_down_312p5_refclk(3:0) In N/A Reference clock inputs for the shared 312.5 MHz oscillator. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_down_jc_refclk(3:0) In N/A Reference clock inputs for the GTH reference clock generated by the jitter cleaner. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_down_sma_refclk(3:0) In N/A Reference clock inputs for the shared front panel SMA connector. IBUFDS_GTE2 instances are already present in fixed logic, so these input ports are already buffered and may be used directly in the CLIP. Each clock signal in the vector is mapped to a GTH Quad in the same order as the TX/RX pairs. For example, refclk(0) should be used for the Quad containing txp/txn/rxp/rxn(3:0), and so on.
ring_down_fpga_ready In Async Signal driven by fixed logic to indicate that all clocks and power supplies required by the FPGA are active and stable.

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