||analog-to-digital converter—A hardware component that converts analog voltages to digitized values. An ADC can convert an analog signal to a digital signal representing equivalent information.||AIO, AIO Module
||An FMC designed for use with the ATCA-3671.
||advanced telecommunications computing architecture
||An HSS protocol typically used for dedicated point-to-point bidirectional communication.
||The interface between the ATCA-3671, RTM, and integrated chassis.
||component-level intellectual property (IP)|
||digital-to-analog converter—An electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current.|
||double data rate type three|
||dual-edge sampling||Diagonal Bus
||Cross-Ring connections between the ATCA FPGAs that do not have Ring Up and Ring Down connections between them. This connection type has a lower bandwidth than Ring Up/Down connections.
||dynamic random access memory—A form of random access memory (RAM). Each bit of information is stored as a charge on a capacitor. This charge must be regularly refreshed to maintain the charge (performed every few milliseconds).|
||first-in-first-out memory buffer—A data buffering technique that functions like a shift register where the oldest values (first in) come out first.|
||FPGA mezzanine card—see AIO.|
||Primary ATCA module inserted in the front of the ATCA chassis.|
||field-programmable gate array—Fundamentally, an FPGA is a semi-conductor device that contains a large quantity of gates (logic devices), which are not interconnected, and whose function is determined by a wiring list, which is downloaded to the FPGA. The wiring list determines how the gates are interconnected, and this interconnection is performed dynamically by turning semiconductor switches on or off to enable the different connections.|
|GbE, 10 GbE
||gigabit, 10 gigabit Ethernet—Used for general purpose high-speed multipoint communication.|
||Transceivers (MGTs) used on the Virtex 7 690T FPGA die. Determine maximum lane rate and data clock jitter characteristics.|
||general-purpose input-output—low-rate parallel digital port. There is a GPIO port attached to each FPGA on the ATCA-3671 module.|
- The SI unit for measurement of frequency. One hertz (Hz) equals one cycle per second.
- The number of scans read or updates written per second.
||high-speed serial—A family of high data-rate serial communication protocols and hardware facilitating the use of those protocols.|
||input/output—The transfer of data to/from a computer system involving communications channels, operator interface devices, and/or data acquisition and control interfaces.|
||The translation of the magnitude and phase data of a signal from a polar coordinate system to a complex Cartesian (X,Y) coordinate system.|
|JESD, JESD 204B
||HSS protocol typically used for unidirectional high-speed communication with a converter (DAC or ADC). Often a parallel interface. ||jitter
||The rapid variation of a clock or sampling frequency from an ideal constant frequency.
||Debugging aid, useful for debugging Microblaze logic.
||One lane of an HSS interface, or one wire on the bus. Often grouped, there are usually multiple lanes per port.|
|lane rate, line rate
||Transmission rate of a serial interface. Often higher than the effective data rate of the interface.|
||Shell extension with preset scripts for hardware configuration and status logging. See Minicom Commands.|
|Mini-SAS, Mini-SAS HD
||Connector standard used in many high-speed serial interfaces.|
||A process, or the result of a process, by which characteristics of a carrier wave are altered according to information in the baseband signal to generate a modulated wave that is transmitted.|
||phase-locked loop—An electronic circuit that controls an oscillator so that the circuit maintains a constant phase angle relative to a reference signal.|
||A physical connector, usually digital. May consist of multiple lanes.|
||quad small form-factor pluggable—Four SFP lanes in one physical port.|
||Clock to which a device phase locks another, usually faster, clock. A common source for the reference clock is the 10 MHz oscillator present on the PXI backplane.|
|Ring, Ring Up, Ring Down
||Abstraction of the connections between the four FPGAs on the ATCA-3671 that represents the symmetrical buses between the FPGAs.|
||radio frequency—Refers to the radio frequency range of the electromagnetic spectrum. RF is often used to describe a range of sub-infrared frequencies from the tens of MHz to several GHz.|
||rear transition module|
||Receive data or signals. RX refers to the hardware receiver; Rx refers to receive operations in software.|
||The rate at which a device acquires an analog signal, expressed in samples per second (S/s). The sample rate is typically the clock speed of the analog-to-digital converter (ADC).|
||small form-factor pluggable transceiver—A connector standard in HSS interfaces|
||A small type of threaded coaxial signal connector. On the ATCA-3671, these connectors provide various signal and I/O capabilities.|
||The destination of a bitfile, bitstream, or compiled application. Typically, this is a specific FPGA in a system.|
||Transmit data or signals. TX refers to the hardware transmitter; Tx refers to transmit operations in software.|
||voltage-controlled oscillator—An oscillator with a frequency determined by a control voltage.|
||voltage-controlled crystal oscillator|