ATCA-3671 Jitter Cleaner Operation

NI-ATCA FPGA Modules Help

Edition Date: September 2018

Part Number: 376468B-01

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Default Mode

By default, the Jitter Cleaner operates in dual PLL with internal VCO mode, as shown in the diagram. In this mode, the Jitter Cleaner propagates a clock signal through two phase locked loops (PLLs) to generate a specific clock rate or clean an existing clock signal.

Jitter Cleaner Diagram


The CLKinX terminal provides input to the Jitter Cleaner. By default, the Jitter Cleaner's clock source is set to the 100 MHz onboard reference clock.

To modify the signal used by the CLKinX, follow the instructions in Configuring the Jitter Cleaner. The input frequency must be specified to the Jitter Cleaner using the ATCA-3671 Configure Jitter Cleaner VI or the minicom jc_set_input_freq command. These commands will change the PLL1 R and N dividers accordingly.


The VCXO is an external oscillator set at 122.88 MHz. The frequency of this oscillator is constant and cannot be configured.


If the Jitter Cleaner will not lock with your current settings, ensure that the jc_set_input command was provided with the actual CLKinX frequency and that the jc_set_vco command was called with 122.88 MHz as the VCXO frequency. If either of these commands is called with a frequency other than the actual signal, the dividers will be set incorrectly and the feedback and reference paths will not match.

If the input frequency and VCXO frequency are set correctly, the clock propagation and feedback paths will be the same frequency at each PLL. You can verify this by reading the R and N divider values from the JC’s registers and plotting out the frequency along each path.

See ATCA-3671 Jitter Cleaning Phase Locked Loop (PLL) or Section 9.1.5 of the LMK0480X Datasheet on to learn more about PLL locking.


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