IMAQ FPGA Pixel Bus to FIFO VI

Owning Palette: Image Transfer
Requires: NI Vision Development Module

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

The data type of the FIFO must match the fundamental data type of the pixel:

  • A U1 or U8 pixel must match a U8 FIFO
  • A U16 pixel must match a U16 FIFO
  • A U32 pixel must match a RGB32 FIFO or HSL32 FIFO

Use the pull-down menu to select an instance of this VI.

IMAQ FPGA Pixel Bus to FIFO U1x1

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U1x1

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO U1x8

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U1x8

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO U8x1

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U8x1

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cu8.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO U8x8

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U8x8

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cu8.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO U16x1

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U16x1

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cu16.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO U16x8

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO U16x8

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cu16.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO RGB32x1

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO RGB32x1

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cnclst.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cu8.gif

A is the value of the alpha plane.

/images/reference/en-XX/help/370281AG-01/cu8.gif

R/H is the red or hue value of the first color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

G/S is the green or saturation value of the second color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

B/L is the blue or luminance value of the third color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO RGB32x8

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO RGB32x8

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cnclst.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cu8.gif

A is the value of the alpha plane.

/images/reference/en-XX/help/370281AG-01/cu8.gif

R/H is the red or hue value of the first color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

G/S is the green or saturation value of the second color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

B/L is the blue or luminance value of the third color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO HSL32x1

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO HSL32x1

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cnclst.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cu8.gif

A is the value of the alpha plane.

/images/reference/en-XX/help/370281AG-01/cu8.gif

R/H is the red or hue value of the first color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

G/S is the green or saturation value of the second color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

B/L is the blue or luminance value of the third color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Pixel Bus to FIFO HSL32x8

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.

IMAQ FPGA Pixel Bus to FIFO HSL32x8

/images/reference/en-XX/help/370281AG-01/ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

/images/reference/en-XX/help/370281AG-01/cnclst.gif

Pixel Data is the value of the pixel.

/images/reference/en-XX/help/370281AG-01/cu8.gif

A is the value of the alpha plane.

/images/reference/en-XX/help/370281AG-01/cu8.gif

R/H is the red or hue value of the first color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

G/S is the green or saturation value of the second color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cu8.gif

B/L is the blue or luminance value of the third color plane, depending on the color mode.

/images/reference/en-XX/help/370281AG-01/cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

/images/reference/en-XX/help/370281AG-01/cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

/images/reference/en-XX/help/370281AG-01/cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

/images/reference/en-XX/help/370281AG-01/cio.gif

Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor.

/images/reference/en-XX/help/370281AG-01/cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

/images/reference/en-XX/help/370281AG-01/ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

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