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Short Name: Update Clock Source
Property of niFgen
Controls the Update Clock source.
|Note You cannot change this property while the device is generating a waveform. If you want to change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete.|
Internal update clock
External update clock given on the IO connector
Coaxial CLK IN connector on the board front panel
DDC CLK IN line of the Digital Data & Control connector
(PXI only) PXI star trigger line. This choice is valid only in PXI chassis slots 3 through 15.
RTSI line 0
RTSI line 1
RTSI line 2
RTSI line 3
RTSI line 4
RTSI line 5
RTSI line 6
(PCI only) RTSI line 7
Uses another device terminal.
The following table lists the characteristics of this property.