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Eight PXI bused trigger lines are highly flexible and can be used in a variety of ways. For example, triggers can be used to synchronize the operation of several different PXI peripheral modules. In other applications, one module can control carefully timed sequences of operations performed on other modules in the system. Triggers may be passed from one module to another, allowing precisely timed responses to asynchronous external events that are being monitored or controlled. The number of triggers that a particular application requires varies with the complexity and number of events involved.
The PXI Specification is implemented with the RTSI bus through the PXI trigger lines. PXI Specification requires 8 lines, PXI_TRIGGER[0:7], on the P2/J2 connector of the PXI chassis for the trigger lines. The RTSI features of the NI Source hardware is implemented on this sub-bus. The RTSI trigger [0..6] is implemented on PXI_TRIGGER[0:6], and the RTSI clock is routed on PXI_TRIGGER(7).