Sample Clock

NI High-Speed Digitizers Help (NI-SCOPE)

Edition Date: January 2017

Part Number: 370592AB-01

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The sample clock is sent to the ADC of each channel and to the acquisition engine to control the sampling rate of a digitizer. The sample clock sources are as follows.

Internal Sample Clock

High-speed digitizers and oscilloscopes have an onboard (internal) clock that controls the sampling rate as well as other timing functionality of the device. In most cases, the onboard oscillator is a Voltage Controlled Crystal Oscillator (VCXO). Typically, an onboard DAC (digital to analog converter) is used to calibrate the VCXO to exactly the desired clock rate. This DAC can also be used to adjust the frequency of the VCXO to phase lock it to a reference clock. The maximum sampling rate of a device is usually determined by the speed of the onboard clock. However, other sampling rates can be achieved by two methods; decimation of the data or dividing down the onboard clock.

Decimation Method

In the decimation method, the ADC samples at the rate of the onboard clock and then sends its digital data to a decimator that essentially discards samples at a specific interval to achieve slower effective sampling rates. The valid sampling rates are always an integer divisor of the onboard clock. For example, if the onboard clock is 100 MHz but you want to sample at 25 MS/s, you must use decimation. The decimation method would discard all data except for every fourth datapoint to achieve exactly 1/4 of the maximum sample rate (or onboard clock rate).

Divide Down Clock Method

Some oscilloscopes use the divide down clock method. In this method the onboard clock is sent through a series of clock dividers, and then that clock is sent to the ADC. Typically, the decimation method is preferred over the divide down clock method.

Note  NI high-speed digitizers support the decimation method but do not support the divide down clock method.

External Sample Clock

Some digitizers and oscilloscopes can accept an external sample clock. This external sample clock is used to replace the onboard clock (the VCXO) for synchronization or to achieve a sampling rate that cannot be specified by using the onboard clock. Some devices can also decimate the external sample clock to achieve a sampling rate that is an integer divisor of the external sample clock. For example, if the external sample clock is 70 MHz, you could decimate the clock by a factor of 2 and achieve a 35 MS/s sampling rate.

Note  Not all devices support the option for an external sample clock and/or decimation of that clock. Refer to Features Supported by Device for more information. If your device does not support external sample clocks, refer to reference clock for another method of synchronization.


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