CAN Advanced Port Configuration

CompactRIO Reference and Procedures (FPGA Interface)

Edition Date: June 2010

Part Number: 370984T-01

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This dialog configures advanced properties for the CAN port. You can display this dialog from the Module Configuration.

Timeouts

The Input Timeout (ms) and Output Timeout (ms) specify timeout values to use with CAN nodes in the FPGA VI block diagram.

Each timeout is a signed 32-bit integer with a resolution of milliseconds, thus allowing a maximum value of approximately 25 days. Special values of 0 (do not wait) and –1 (wait indefinitely) are supported.

The CAN Input function waits for a new CAN frame to be received, then returns that frame. The Input Timeout (ms) specifies how long to wait for a new frame to be received.

If you specify Input Timeout (ms) of 0, the CAN Input node will simply check to see if a new frame has arrived (non-blocking). If a new frame exists, CAN Input returns the frame with an error status of FALSE (success). If no new frame exists, CAN Input returns an error status of TRUE (error). Therefore, in order to poll for new frames using an input timeout of 0, you must enable Error Terminals for the CAN Input node. When an error is returned, you must invoke CAN Input again at a later time to ensure no data is lost.

The communication path from LabVIEW FPGA to the CAN port is implemented as a FIFO. This allows multiple frames to be sent to the CAN module for transmit, thus enabling VIs that generate full bus load.

When the output FIFO is full, the CAN Output node waits for an element to become available, then writes the frame to the FIFO. Output Timeout (ms) specifies how long to wait for a new element to become available, which occurs when a frame from a previous CAN Output transmits successfully onto the network. If you specify Output Timeout (ms) of 0, the CAN Output node returns an error status of TRUE (error) if a new element is not available in the FIFO (non-blocking). When an error is returned, you must attempt CAN Output of the same frame again at a later time.

In addition to the CAN Output node, Output Timeout (ms) also applies to most methods and properties. For example, if Output Timeout (ms) is 0, the Abort Transmit method returns an error if the output FIFO is full. Refer to the Arbitration topic for more information on the output path from LabVIEW FPGA to the CAN port.

Bit Timing

When Specify Baud Rate as Bit Timing Registers is FALSE (unchecked), the baud rate for the CAN port is selected using the Baud Rate in the Module Configuration dialog box. The SJA1000 bit timing registers for the corresponding baud rate are grayed out.

When Specify Baud Rate as Bit Timing Registers is TRUE (checked), the Baud Rate in the Module Configuration dialog box is ignored, and two integer controls BTR0 and BTR1 set the baud rate for the CAN port. The values for BTR0 and BTR1 are specified as hexadecimal. For information on CAN bit timing registers, refer to the datasheet of the Philips SJA1000 standalone CAN controller, available for download on www.philips.com.

Input Filter

This selection controls the acceptance filter registers of the SJA1000 CAN controller. The acceptance filter enables the SJA1000 to filter out certain CAN frames so that your FPGA VI can work with reduced overall traffic. The acceptance filter applies only to received frames, not transmitted frames.

The Input Filter selection determines how you specify the filter values in the dialog box:

Receive All

Receive all frames (all identifiers). This value is the default.

Register values corresponding to reception of all identifiers are shown in SJA1000 Filter Mode, SJA1000 Mask, and SJA1000 Code (grayed).

Receive Selected

Receive frames with selected identifiers. Based on a list of identifiers that you enter, the dialog will calculate values for the SJA1000 filter registers. The calculation attempts to filter out as many unwanted IDs as possible.

You select the list of identifiers using the following controls:

ID Format

Selects whether your CAN network uses Standard identifiers (11-bit) or Extended identifiers (29-bit).

ID Display

Selects whether to use Decimal or Hexadecimal for the identifiers in the Add control and Selected IDs list.

Add From Database

Opens a file dialog from which you can select a CANdb file (.DBC) or an NI-CAN database file (.NCD). When you click the OK button in the file dialog, the identifiers for all messages in the database are added to the Selected IDs.

The Add From Database button requires features of NI-CAN 2.3 or higher in order to import identifiers. If you do not have NI-CAN 2.3 or higher installed on your Windows system, the Add From Database button is grayed out.

Add

Enter a single identifier using the control to the right, then click this button to add the identifier to the Selected IDs.

Delete

Select a single identifier within the Selected IDs list, then click this button to delete that identifier from the list.

Delete All

Deletes all identifiers in Selected IDs.

Selected IDs

List of identifiers that you have selected using controls to the left. The dialog calculates the SJA1000 filters from this list, and the resulting register values are shown in SJA1000 Filter Mode, SJA1000 Mask, and SJA1000 Code (grayed).

If you change the Input Filter from Receive Selected to SJA1000 Format, the register values in SJA1000 Filter Mode, SJA1000 Mask, and SJA1000 Code retain their calculated values. This allows you to use Receive Selected to calculate filters for the identifiers, then change the registers directly for advanced filtering, such as checks for patterns in the data bytes.

Number of Unwanted IDs

Given the current filter calculation, this displays the number of identifiers that your FPGA VI will receive which are not listed in Selected IDs. Since the SJA1000 registers filter using bitwise masking, the filter efficiency is rarely 100%. If you use ID Format of Extended, this number can be large due to the 29 total bits used for identifiers.

SJA1000 Format

With this selection, you use controls to set the SJA1000 registers directly. For information on the SJA1000 acceptance filter registers (PeliCAN mode), refer to the datasheet of the Philips SJA1000 standalone CAN controller, available for download on www.philips.com.

SJA1000 Filter Mode

Controls the Acceptance Filter Mode bit of the SJA1000 Mode register. Dual (0) specifies use of two filters, and Single (1) specifies use of a single filter.

SJA1000 Mask

Controls the SJA1000 Acceptance Mask 0–3 registers. The value is specified as hexadecimal. The least significant byte of the value is stored in register offset 3 (AMR3), the next least significant in offset 2 (AMR2), and so on.

SJA1000 Code

Controls the SJA1000 Acceptance Code 0–3 registers. The value is specified as hexadecimal. The least significant byte of the value is stored in register offset 3 (ACR3), the next least significant in offset 2 (ACR2), and so on.

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