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The LabVIEW Simulation Interface Toolkit ships with FPGA bitfiles for many National Instruments R Series Intelligent DAQ devices. These VIs and bitfiles define the analog, digital, and pulse width modulation (PWM) inputs and outputs of the FPGA target. You use this information to create mappings between a model DLL and one or more FPGA targets. The Simulation Interface Toolkit also ships with a project file you can use with the NI cRIO-9103 chassis.
These default bitfiles are sufficient for many applications. However, in some situations, you might need to create a custom FPGA bitfile to use with a simulation. For example, if you want to use additional digital I/O lines, more than two PWM outputs, or digital filtering built into the FPGA, you must create a custom bitfile. If you are running a simulation on a CompactRIO chassis, you also must create a custom bitfile, because CompactRIO chassis do not contain any built-in I/O modules. You must install the LabVIEW FPGA Module to create these files.
The following sections provide information about creating a custom FPGA bitfile.
Creating a custom FPGA bitfile includes the following three steps:
The first step is to make a copy of a default FPGA VI and project. This step is different depending on whether you are using an R Series device or a CompactRIO chassis.
The next step is customizing the FPGA VI.
The next step is customizing the FPGA VI.
The process of creating the custom FPGA VI differs depending on the hardware devices you are using. Refer to the FPGA Module documentation for information about creating FPGA VIs and bitfiles for an FPGA target.
The default project defines the following FPGA I/O items for the PXI-7831R device: analog input channels 0–7, analog output channels 0–7, and digital lines 0–39 on both connectors 1 and 2 and digital line 0—15 on connector 0. You can add or remove FPGA I/O items depending on the device and the needs of the simulation. For example, the PXI-7811R device has 160 DIO lines available; however, by default this sample FPGA VI uses only the first 40 lines on connectors 1 and 2. You can add more FPGA I/O items to this project if you want to use the additional DIO lines available on the PXI-7811R. Conversely, the PXI-7811R has no analog inputs or outputs, so if you are using this device, you can remove the analog I/O items from the project and the corresponding FPGA I/O Nodes from the FPGA VI.
Similarly, the default sample FPGA VI defines the digital lines on connector 0 as 8 PWM inputs and 8 PWM outputs. You might want more or fewer PWM channels. You might also add other custom I/O not defined in the sample FPGA VI.
|Note��The driver VI converts analog, digital, and PWM information to double-precision, floating-point numbers for greater accuracy and precision on Windows computers and RT targets. You can avoid this conversion by creating an FPGA VI that transmits this information by using fixed-point numbers. For more information about how SIT handles data types on FPGA, refer to Representing Data Types on FPGA Targets.|
If you created a new target for an R Series device, you can drag the FPGA I/O folders from the original PXI-7831R (PXI-7831R) target to the new target. The FPGA VI shows broken wires from any FPGA I/O Nodes with undefined channels.
(CompactRIO Chassis) If you are using the existing cRIO-9103 target, the project defines an NI 9215 module for analog input, an NI 9263 module for analog output, an NI 9411 module for digital input, and an NI 9474 module for digital output. You can delete or modify these modules based on the ones you are using for the simulation. If you need to add modules to the target, or if you created a new target, you can add the necessary modules by right-clicking the target and selecting New�C Series Modules.
|Note��In the sit IO cRIO.vi example, the FPGA I/O mode calibrates the analog input and analog output channels of the NI 9215 and NI 9263 modules. The host VI running on the CompactRIO real-time controller returns the data as a scaled fixed-point value.|
|Note��Refer to the National Instruments Web site for information about these devices and modules.|
While you are creating/modifying the FPGA VI, pay attention to the following guidelines to ensure the SIT Connection Manager dialog box recognizes this FPGA VI.
When you are finished creating the FPGA VI, select File�Save to save this VI.
The next step is compiling the custom FPGA VI into a bitfile.
Complete the following steps to compile the custom FPGA VI and create the bitfile.
The next step is using the SIT Connection Manager dialog box to create mappings between the model DLL and the FPGA target.
As you create mappings, you associate the custom FPGA bitfile you created with the appropriate FPGA target. You then can create mappings between the model DLL and the FPGA target using the custom FPGA VI you created.
|Tip�� If the bitfile does not show up, it is likely that it does not follow the naming conventions listed above or that it is not in the correct directory.|