NI PXI-7842R Reference

NI R Series Multifunction RIO Device Drivers Help

Edition Date: May 2018

Part Number: 371508V-01

»View Product Info
Download Help (Windows Only)

R Series Reconfigurable I/O Module (AI, AO, DIO)

8 AI channels, 8 AO channels, 96 DIO lines, LX50, 200 kS/s AI Sample Rate

FPGA I/O Node

You can use an FPGA I/O Node, configured for reading and writing, with this device.

Note  FPGA I/O Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line.

Terminals in Software

You can select the following terminals for this device.

Note Note  In LabVIEW 8.6.1 and earlier, some terminal names appear differently. Refer to Terminal Name Conversion for R Series Devices for a list of affected terminal names.


Terminal Description
AIx Analog input channel x, where x is the channel number. Use an FPGA I/O Node configured for reading to access this channel.
AOx Analog output channel x, where x is the channel number. Use an FPGA I/O Node configured for writing to access this channel.
Connectorx/DIOy Digital input/output channel y on connector x, where y is the channel number and x is the connector number. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this channel.
Connectorx/DIOPORTy Digital input/output port y on connector x, where y is the port number and x is the connector number. A port is made up of eight digital channels. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this port.
PXI/PXI_Clk10 10 MHz clock in the PXI chassis that you can use to synchronize multiple PXI modules. Use an FPGA I/O Node configured for reading to access this channel.
Note  You can phase-lock the FPGA device clock to the 10 MHz clock of the PXI chassis. Select Start»All Programs»NI»RIO Device Setup to launch the RIO Device Setup utility, which you can use to synchronize the FPGA clock to the 10 MHz clock of the PXI chassis. The FPGA clock itself does not change to 10 MHz even though you synchronize it.
PXI/PXI_Star Star trigger bus. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this channel.
Caution  Do not use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable to access the PXI/PXI_Star channel if the FPGA device is in Slot 2 of the PXI chassis. Writing to the PXI/PXI_Star channel when the FPGA device is in Slot 2 affects the accuracy of the 10 MHz clock and can cause the PXI system to malfunction.
PXI/PXI_Trigx Trigger channel x, where x is the channel number <0..7>. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this channel. Follow the guidelines for using PXI triggers with the LabVIEW FPGA Module.
Board IO/Device Temperature Returns the current temperature of the device, in increments of 0.25 °C. The temperature is measured from an onboard temperature sensor on the device PCB, external to the FPGA.

In this format, device temperature = (Returned Device Temperature decimal value) ´ 0.25 °C. For example, a returned Device Temperature decimal value of 120 would indicate a device temperature of 30 °C.

Arbitration

This device supports arbitration. Configure the arbitration settings for the channels of this device in the FPGA I/O Properties dialog box for the FPGA I/O item you are using.

I/O Methods

Use the FPGA I/O Method Node to invoke methods. You can use the following methods with this device.

Note  FPGA I/O Method Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line.

Method Description
Set Output Data Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.
Set Output Enable Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.
Wait on Any Edge Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Falling Edge Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on High Level Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Low Level Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Rising Edge Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.

I/O Properties

This device does not support any properties.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only.

WAS THIS ARTICLE HELPFUL?

Not Helpful