Clear (FIFO Method)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Clears a target-scoped or VI-defined FIFO on the FPGA.

You cannot use this method with DMA FIFOs or peer-to-peer FIFOs. To clear DMA FIFOs from the host VI, use the Stop method on the Invoke Method function. To clear peer-to-peer FIFOs, use the Peer-to-peer streaming VIs and functions.

Use the FIFO Method Node to implement this method.


FIFO In specifies the FIFO. You can wire a FIFO control, FIFO constant, VI-Defined FIFO Configuration node, or the FIFO Out terminal of another FIFO Method Node to FIFO In.
FIFO Out returns FIFO In if FIFO In is wired. Otherwise, FIFO Out returns the FIFO that you specify in the FIFO Method Node.

Clear (FIFO Method) Details

The following types of FIFOs support this method:

  • Target-scoped
  • VI-defined

Considerations for Single-Cycle Timed Loops

You cannot use the Clear method inside a single-cycle Timed Loop. However, when FIFOs are configured as Block Memory, you can use the Clear method in the top-level clock domain, even if the top-level clock domain is different than the clock domain(s) specified by the single-cycle Timed Loop(s) in which the FIFO Write and Read methods are used.

Considerations When Using the Clear Method with Built-in FIFOs

If the FIFO uses built-in controller logic, the Clear method takes multiple clock cycles because it clears elements one by one instead of simultaneously. The Clear method also increases resource usage and may reduce the maximum frequency of the clock domain that contains the FIFO.


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