Read (FIFO Method)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Reads and removes the oldest element(s) from the FPGA FIFO. Configure the number of elements per read from the Interfaces page of the FIFO Properties dialog box.

Use the FIFO Method Node to implement this method.

The input and outputs available for this method depend on if you select the timeout or handshaking interface.

Details  

FIFO In specifies the FIFO. You can wire a FIFO control, FIFO constant, VI-Defined FIFO Configuration node, or the FIFO Out terminal of another FIFO Method Node to FIFO In.
Timeout specifies the time, in number of clock ticks, that the method waits for available data in the FIFO if the FIFO is empty. A value of –1 prevents the function from timing out, so the function completes execution only when data is available for reading. A value of 0 indicates that the function does not wait. Wire a constant of 0 to Timeout if you use the FIFO Method Node in a single-cycle Timed Loop.

This input is the default for the Read method. To display this input, right-click the Read method and select Interface»Timeout from the shortcut menu.
FIFO Out returns FIFO In if FIFO In is wired. Otherwise, FIFO Out returns the FIFO that you specify in the FIFO Method Node.
Element returns the oldest data element or elements in the FIFO. The Element data type is the data type you configure in the FIFO Properties dialog box when you create the FIFO. If the FIFO is empty, Element is undefined and no read occurs.
Timed Out? returns TRUE if an element is not available in the FIFO before the function completes execution. If Timed Out? is TRUE, Element is undefined and no read occurs.
Note  (Xilinx Vivado) In simulation mode, if the FIFO is implemented with the built-in control logic, the Timed Out? value might not reflect the actual behavior on hardware because this method uses Actual Number of Elements in the General Page of the FIFO Properties dialog box as the FIFO depth, which might be smaller than the actual number of elements in the FIFO.
This output is the default for the Read method. To display this output, right-click the Read method and select Interface»Timeout from the shortcut menu.
Ready for Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
Note  If Ready for Output is FALSE during a given cycle, the Output Valid terminal returns FALSE during the given cycle.

To display this handshaking terminal, right-click the Read method within a single-cycle Timed Loop and select Interface»Handshaking from the shortcut menu.
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from this node to the downstream node.

To display this handshaking terminal, right-click the Read method within a single-cycle Timed Loop and select Interface»Handshaking from the shortcut menu.

Read (FIFO Method) Details

If you use this method in a single-cycle Timed Loop, you must set the Read option on the Interfaces page of the FIFO Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate for the FIFO item you read. When you set the Read option to Arbitrate if Multiple Requestors Only, you cannot use multiple FIFO Method Nodes configured with the Read method to access the same FIFO in the FPGA VI.

If you enable the timeout interface for this method within a single-cycle Timed Loop, you also must wire a constant of 0 to Timeout. If the FIFO is empty, the method executes and returns a timeout instead of valid data. The method continues to return a timeout until data is available to read.

You can use the handshaking interface only within a single-cycle Timed Loop. Additionally, some targets do not support the handshaking interface for peer-to-peer and DMA FIFOs. LabVIEW returns a compile time error for FIFOs that do not support the handshaking interface.

You can use FIFOs to transfer data among multiple clock domains.

Related Information

Understanding Arbitration Options

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