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Requires: FPGA Module
Flushes a peer-to-peer writer FIFO and then disables the peer-to-peer writer and reader FIFOs in a peer-to-peer streaming session. Wiring either a writer or reader FIFO to this node disables both the writer and reader in the streaming session. This method writes all data from the writer FIFO to the reader FIFO before disabling the FIFOs. To flush a peer-to-peer writer FIFO without disabling the writer and reader FIFOs, use the Flush method. To disable the FIFOs without flushing the writer, use the Disable method.
This node waits until both the writer and reader FIFOs are disabled. If the peer-to-peer stream is already in a disabled or unlinked state, this node does nothing. The Flush and Disable method does not clear data in the reader FIFO. Therefore, you can read any data left in the reader FIFO after this node runs and the peer-to-peer stream is disabled.
This method is only available with peer-to-peer FIFOs. Use the FIFO Method Node to implement this method.
|FIFO In specifies the FIFO. You can wire a FIFO control, FIFO constant, VI-Defined FIFO Configuration node, or the FIFO Out terminal of another FIFO Method Node to FIFO In.|
|Timeout specifies the time, in number of clock ticks, that the method waits to flush all data from the writer FIFO and write the data to the reader FIFO. A Timeout value of –1 waits indefinitely for the flush to complete. A value of 0 specifies that this node does not wait. A value greater or equal to 1 specifies the number of clock cycles to wait for the flush to complete. If the flush does not finish before the Timeout value, Timed out? returns TRUE.|
|FIFO Out returns FIFO In if FIFO In is wired. Otherwise, FIFO Out returns the FIFO that you specify in the FIFO Method Node.|
|Timed Out? returns TRUE if the flush did not complete before the time limit. Otherwise, Timed Out? is FALSE. If Timed Out? is TRUE, data remaining in the writer FIFO is lost.|
Because this node waits until the peer-to-peer writer and reader FIFOs are disabled, you cannot use this node in a single-cycle Timed Loop. If you use this node in a single-cycle Timed Loop, LabVIEW reports a code generation error when you try to compile the FPGA VI.