Notch Filter Express VI

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Owning Palette: FPGA Math & Analysis VIs and Functions

Requires: FPGA Module

Attenuates a specific frequency band in one or more input signals using a second order IIR notch filter.

You can use the Notch Coefficients Express VI to generate the set of filter coefficients during run time.

Details  Examples

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Filter SpecificationsContains the following options:
  • Notch frequency (Hz)—Specifies the center frequency for the notch filter to attenuate.
  • Expected sample rate (S/s)—Specifies the sample rate of the input signal. This Express VI uses the rate you specify to calculate the normalized notch frequency, which is Notch frequency/Expected sample rate.
    Caution  The actual sample rate is specified elsewhere in the FPGA application. If the sample rate changes, you must change the Expected sample rate in this VI. Otherwise, this VI might not behave as expected.
  • Specify quality—Allows you to configure the Q factor of the notch filter.
    • Q factor—Specifies the quality factor of the notch filter. This option is available only when you select Specify quality.
  • Specify bandwidth—Allows you to configure the Notch width (Hz) of the notch filter.
    • Notch width (Hz)—Specifies the 3-dB bandwidth of the filter, which is the frequency range for which the filter attenuates the signal energy by a factor of two or more. This option is available only when you select Specify bandwidth.
Output Data TypeContains the following options:
  • Avoid overflow—Specifies that the word length and integer word length of the output data type are large enough to ensure that the filter output does not overflow.
  • Same as input—Specifies that the output data type is the same as the input data type. The output will saturate if the output range is exceeded during signal transients. Overflow will not occur with a steady-state sinusoidal input.
ImplementationContains the following options:
  • Number of channels—Specifies the number of channels of input data to process. The calling VI must supply a sequential channel scan to input data on successive calls to this Express VI. The channel order must be fixed.
  • FPGA clock rate (MHz)—Specifies the clock rate at which LabVIEW compiles the FPGA VI. If the FPGA clock rate parameter does not match the top-level clock rate, the Code Generation Errors window returns an error when you compile the FPGA VI. Use the Top-Level Clock FPGA Target Properties page to change the top-level clock rate.
Filter ResponseDisplays the actual magnitude response of the filter.

Block Diagram Inputs

ParameterDescription
resetResets the filter state of the input data channel to zero if TRUE. Resetting the filter state does not reset the filter coefficients. This Express VI resets automatically the first time you call it.
input dataSpecifies the input signal to filter. input data is a fixed-point number or integer with a maximum word length of 32 bits.
scaled coefficientsSpecifies single-channel filter coefficients to load at run time. Scaled coefficients is a fixed-size array of three 32-bit signed integers.

This parameter is available only when you configure the VI for single-channel input in the configuration dialog box.
configurationSpecifies the scaled coefficients to load at run time for the channel index you specify using the channel index element of this cluster. This Express VI continues to use either the default coefficients or the last coefficients you specified for the channel until you specify new coefficients. This parameter is available only when you configure the VI for multi-channel input in the configuration dialog box.

Block Diagram Outputs

ParameterDescription
output dataReturns the filtered signal corresponding to the input data channel.

Notch Filter Details

You can configure the sharpness of the notch by specifying either the Notch width or the Q factor of the filter. To use Notch width, select Specify bandwidth in the Filter Specifications section of the configuration dialog box. To use Q factor, select Specify quality in the Filter Specifications section of the configuration dialog box.

Q factor and Notch width are related by the following equation:

Q factor = Notch frequency/Notch width.

Notch frequency and Notch width or Q factor are constrained such that the upper end of the attenuated frequency band is less than half of the Expected sample rate (S/s) (Nyquist frequency) and the lower end of the attenuated frequency range is greater than zero (DC).

Refer to the support document at ni.com for more information about the accuracy of the FPGA Math and Analysis VIs.

Examples

Refer to the following VIs for examples of using the Notch Filter Express VI:

  • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\Notch Filter\Notch Filter.lvproj
  • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\Notch Filter\Notch Filter.lvproj

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