Write I/O Function

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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Owning Palette: User-Controlled I/O Sampling Functions

Requires: FPGA Module

Writes new output data to the I/O items as soon as the target is ready to receive new data. This function does not overwrite previously written data.

The following connector pane displays the parameters that appear when this function is outside a single-cycle Timed Loop.


error in describes error conditions that occur before this node runs. This input provides standard error in functionality. If error in does not equal No Error, the value of error in passes to error out and this function does not execute.
FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.
I/O Item is the data to write to the FPGA I/O item.

When you select an element on the node without wiring a value to FPGA I/O In, the name of this parameter changes to match the name of the FPGA I/O item you specify.
Timeout specifies the maximum time, in number of clock ticks, that the function waits until it can write to an I/O item without overwriting data. A value of –1 prevents the function from timing out, so the function completes execution only when it writes all data. If Timeout is 0 and this function cannot write data immediately, a timeout occurs. If a timeout occurs, previously written data remains intact.
Input Valid specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

To display this handshaking terminal, right-click the function and select Inside single-cycle Timed Loop from the shortcut menu.
error out contains error information. This output provides standard error out functionality.
FPGA I/O Out returns the FPGA I/O In.
Timed Out returns TRUE if this function times out. If Timed Out is TRUE, this function did not write data to any I/O items.
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.
To display this terminal, right-click the function and select Inside single-cycle Timed Loop from the shortcut menu.

Write I/O Details

Not all targets support the User-Controlled I/O Sampling functions.

To select a method, first configure the node with an I/O item.

This function writes data to a buffer on the FPGA. Once this function writes data to the buffer, the data transfers from the buffer to the I/O item. Once the Generate I/O Sample Method executes, the I/O item can output the data. Data transfers to the I/O item either immediately if the item has space available or after the Generate I/O Sample Pulse Method executes if no space is available. Use the Get I/O Write Status Method function to determine when the data has transferred to the I/O item.

If multiple Write I/O Method functions contain the same I/O item, all functions reference the same data buffer. If the buffer is empty when the Generate I/O Sample Pulse Method function executes, the buffer regenerates and the previously written data is transferred again. If multiple I/O Items in the same node are present, the write will occur only if each I/O Item has space available. Otherwise, a timeout will be reported.

Single-Cycle Timed Loop Details

This node is supported inside and outside the single-cycle Timed Loop if the target supports it. Right-click the function and select Execution Mode»Outside single-cycle Timed Loop or Inside single-cycle Timed Loop to specify where the function executes.

Error Handling Details

You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.


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