|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Owning Palette: Timed Structures
Requires: FPGA Module
Use the FPGA clock constant to specify an FPGA clock on the block diagram.
The shortcut menu that appears when you click the arrow button on the right of the constant lists the clocks that appear in the Project Explorer window under the same FPGA target as the active VI. To use an FPGA clock that is not already in the project, first add the FPGA base clock, derived clock, or component-level IP (CLIP) clock to the Project Explorer window.
You also can specify an FPGA clock by clicking inside the constant and typing the name of the clock.
When creating a reusable subVI, use the FPGA clock control to specify an FPGA clock on the block diagram.
|Note Although the FPGA clock constant looks the same as the FPGA I/O constant, the two constants represent distinct data types.|