|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Owning Palette: FPGA I/O Functions
Requires: FPGA Module
Invokes a method on an I/O item or hardware under an FPGA target in the Project Explorer window, such as a C Series module. In some cases, you also can invoke methods on the FPGA target itself. The methods available depend on the FPGA target and the FPGA I/O item or C Series module you select.
To select a method, first configure the FPGA I/O Method Node with an item.
|FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.|
|FPGA I/O Out returns the FPGA I/O item on which you configure the node to operate.|
|Tip Right-click the FPGA I/O Method Node and select Find Item in Project from the shortcut menu to highlight the I/O item in the Project Explorer window.|
Additional parameters vary depending on the related method. Method support varies by FPGA target and I/O resource. Some FPGA targets do not support any methods. A method can have zero or more parameters.
FPGA targets with bidirectional digital I/O lines and ports typically support the following methods for bidirectional I/O items.
Error Handling Details
You can right-click the FPGA I/O Method Node on the block diagram and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.
|Note Adding error in and error out parameters may increase the amount of space the function uses on the FPGA target. The error in and error out parameters also may cause slower execution on the FPGA target.|