Rational Resampler Express VI

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Provides a rational resampling filter, which updates the input sample rate by an L/M factor where L is an interpolation factor and M is a decimation factor. Rational resampling is the process of converting the sample rate of a signal to another sample rate that differs from the original sample rate by a rational factor of L/M, where both L and M are integer values. When L=1 and M>1, the resampling is an integer decimation, and when L>1 and M=1, the resampling is an integer interpolation.

Rational resampling is useful for interfacing with digital signal processing (DSP) systems that operate at different sample rates. By choosing L and M properly, you can approximate any desired sample rate change ratio.

Details  

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Filter ParametersContains the following options:
  • L—Specifies the interpolation factor.
  • M—Specifies the decimation factor.
    Note  L and M must never be equal.
  • Stopband attenuation—Specifies the attenuation above where the gain versus frequency has finished its rapid falloff. The default is 80 dB.
  • Input sample rate—Specifies the sample rate of each input channel. The Input sample rate, combined with L and M, determines the Output sample rate.
  • Output sample rate—Indicates the calculated average rate at which the Express VI returns valid output data for each channel.
ImplementationContains the following options:
  • Number of channels—Specifies the number of source channels that this Express VI handles.
  • Adapt to source—Specifies whether this Express VI decides the output data type. Disable the Adapt to source checkbox if you want to use Word length to determine the output data type.
  • Word length—Specifies any output word length in the range of [1, 32]. Word length is available only if you disable the Adapt to source checkbox.
  • Integer word length—Indicates the output integer word length that this Express VI calculates.
  • Show reset terminal—Specifies whether this Express VI includes a reset input on the block diagram to reset this Express VI at run time. You can save resources on the FPGA if you do not enable the Show reset terminal checkbox.
Filter ResponseDisplays the actual magnitude response of the filter.
Execution ModeContains the following options:
  • Outside single-cycle Timed Loop—Select this option to use this Express VI outside of a single-cycle Timed Loop. Outside single-cycle Timed Loop is disabled when L/M is greater than 1.
  • Inside single-cycle Timed Loop—Select this option to use this Express VI inside a single-cycle Timed Loop. Selecting Inside single-cycle Timed Loop enables Throughput. When you execute this Express VI inside the single-cycle Timed Loop, the Express VI provides four handshaking signals you can use to schedule the timing of data. This option is useful if you want to achieve higher throughput using a rational resampling filter.
  • Clock rate—Specifies the level of pipelining stages this Express VI uses internally. Increasing the number of stages increases the clock rate at which this Express VI can compile for both Inside the single-cycle Timed Loop and Outside the single-cycle Timed Loop. This option does not set the clock rate explicitly.
    Note  Adjusting the value of Clock rate increases the FPGA resource usage and latency of this Express VI. An increased latency indicates that this Express VI takes longer to return a valid result.
  • Throughput—Displays the minimum number of cycles between two successive frames of valid input data. LabVIEW sets the value of Throughput according to the options you specify in the configuration dialog box.

    Throughput is available only if you select Inside single-cycle Timed Loop. If you select Outside single-cycle Timed Loop, LabVIEW sets the throughput to 1 call / sample, which means that this Express VI can accept data every time it is called.
Configuration FeedbackDisplays information about how this Express VI executes. This information is based on the configuration options you specify. LabVIEW displays this information only if you select Outside single-cycle Timed Loop.

Block Diagram Inputs

ParameterDescription
resetResets the state of the internal resampling filter. Outside the single-cycle Timed Loop, the Express VI restarts on the same call that reset is TRUE. Inside the single-cycle Timed Loop, the Express VI restarts on the first call that reset is deasserted after reset is TRUE. Additionally, the handshaking signals behave as follows during the cycles where reset is asserted:
  • input valid is ignored.
  • ready for output is ignored.
  • output valid is FALSE.
  • ready for input is FALSE, which handles cases where reset is held TRUE for a long time. The Express VI is not ready for inputs when reset is asserted.
input dataSpecifies the data you want to filter.
input validSpecifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.
ready for outputSpecifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.
Note  If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.
To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

Block Diagram Outputs

ParameterDescription
channel indexIndicates the index of the channel corresponding to the last valid output data.
output dataReturns the filtered data.
output validReturns TRUE if this Express VI has computed a result that downstream nodes can use. Wire output valid to input valid of a downstream node to transfer data from this Express VI to a downstream node. To display output valid, select Inside single-cycle Timed Loop in the configuration dialog box.
ready for inputReturns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.
Note  If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.
To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.

Rational Resampler Details

This Express VI supports handshaking with multiple channels.

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