|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Owning Palette: Timed Structures
Requires: FPGA Module
Starts disabling an FPGA clock to protect circuitry dependent on a periodic clock. Use this VI to disable the clock prior to glitches or before the clock signal becomes unavailable. Clocks that support and require enabling and disabling at run time begin disabled after you download or reset the FPGA VI. When you reenable the clock using the Start Enabling FPGA Clock VI, the state of all registers and memory using the disabled clock is the same as the last cycle before the clock was disabled.
You must include the Start Disabling FPGA Clock VI outside of the single-cycle Timed Loop that is using the clock you are disabling.
|Note CLIP clocks do not support the Start Disabling FPGA Clock VI.|
|FPGA Clock to Disable specifies the clock to disable. The clock you specify must support disabling at run time. To configure a clock to support disabling, place a checkmark in the Supports and Requires Runtime Enable/Disable checkbox in the FPGA Base Clock Properties dialog box.|
|error in describes error conditions that occur before this node runs. With the following exception, this input provides standard error in functionality. |
FPGA VIs do not support the Simple Error Handler VI, General Error Handler VI, or exception control.
|error out contains error information. This output provides standard error out functionality.|
|Single-Cycle Timed Loop||Supported.|
|Usage||You must configure the FPGA VI to execute the Start Disabling FPGA Clock and Start Enabling FPGA Clock VIs at different times. |
The Start Disabling FPGA Clock VI has no effect when you run an FPGA VI on a development computer or use the VI on a non-FPGA target.
|Timing||A short delay exists before the clock is actually disabled because the disable must go through one register in the clock domain where the Start Disabling FPGA Clock VI is running and two registers in the clock domain you want to disable.|
|Resources||This VI consumes minimal FPGA resources.|