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Owning Palette: Timed Structures
Requires: FPGA Module
Starts enabling an FPGA clock. To ensure data integrity, the clock you want to enable must be glitch free and free running. When you reenable the clock using this VI, the state of all registers and memory using the disabled clock is the same as the last cycle before the clock was disabled.
You must include the Start Enabling FPGA Clock VI outside of the single-cycle Timed Loop that is using the clock you are enabling.
|Note CLIP clocks do not support the Start Enabling FPGA Clock VI.|
|FPGA Clock to Enable specifies the clock to enable. The clock you specify must support enabling at run time. To configure a clock to support enabling, place a checkmark in the Supports and Requires Runtime Enable/Disable checkbox in the FPGA Base Clock Properties dialog box. If you place a checkmark in this checkbox, the FPGA Module disables the clock when you download or reset the FPGA VI.|
|error in describes error conditions that occur before this node runs. With the following exception, this input provides standard error in functionality. |
FPGA VIs do not support the Simple Error Handler VI, General Error Handler VI, or exception control.
|error out contains error information. This output provides standard error out functionality.|
|Single-Cycle Timed Loop||Supported.|
|Usage||You must configure the FPGA VI to execute the Start Enabling FPGA Clock and Start Disabling FPGA Clock VIs at different times. |
The Start Enabling FPGA Clock VI has no effect when you run an FPGA VI on a development computer or use the VI on a non-FPGA target.
|Timing||A short delay exists before the clock is actually enabled because the enable must go through one register in the clock domain where the Start Enabling FPGA Clock VI is running and two registers in the clock domain you want to enable.|
|Resources||This VI consumes minimal FPGA resources.|