Adding Component-Level IP to a Project (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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You add a component-level IP (CLIP) item to the LabVIEW project to instantiate the CLIP inside the FPGA. If you want to instantiate the CLIP multiple times, each CLIP instance must have a unique name, and each name must follow VHDL naming conventions. Name each CLIP constant uniquely, and do not prefix CLIP constant names with k.

To add a CLIP item to the LabVIEW project you must associate a CLIP declaration file to the target and then add a CLIP item from the declaration file to the project. You associate a CLIP declaration file to the target using the Component-Level IP page of the FPGA Target Properties dialog box. You add the CLIP item to the project using the General page of the Component-Level IP Properties dialog box. Use the Clock Selections page of the Component-Level IP Properties dialog box to link clocks from the FPGA target to the inputs of the CLIP.

To pass data between CLIP and an FPGA VI, the CLIP declaration file must have a <InterfaceType>LabVIEW</InterfaceType> tag. Then, when you add the CLIP item to a LabVIEW project, the FPGA Module adds all of the I/O that is defined in the declaration XML file under the CLIP item in the LabVIEW project.

Tip  Use the CLIP wizard to create the necessary interface in the declaration file. The CLIP wizard automatically adds the CLIP to the project when you finish it.

Refer to the CLIP Tutorial, Part 3: Adding CLIP to a Project for an example of adding CLIP to a Project.

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