|LabVIEW 2016 FPGA Module Help|
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|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
The following arbitration options are available with the FPGA Module:
An arbiter performs the following general steps during arbitration.
|Note The order in which an arbiter grants access to multiple requestors is non-deterministic.|
Arbitration requires significant space on the FPGA. If you can decrease the number of requestors of a resource interface to one in the entire FPGA VI hierarchy, use the Arbitrate if Multiple Requestors Only or Never Arbitrate arbitration options. The single requestor requires no arbitration.
A resource interface with the Always Arbitrate option always uses an arbiter, even if only one requestor requests access. The Always Arbitrate arbiter is a fair round robin arbiter that ensures sequential access to a shared resource. The arbiter does not allow a requestor to become an accessor again until all other waiting requestors have become accessors. Consequently, jitter occurs if you have more than one simultaneous requestor.
Use the Always Arbitrate option if you need single requestor channels synchronized with multiple requestor channels. Refer to Timing FPGA VIs with Arbitration Enabled for information about synchronized channels.
A resource interface with the Arbitrate if Multiple Requestors Only option does not use an arbiter if the FPGA VI contains only one requestor. If the resource interface has multiple requestors, LabVIEW generates arbitration circuits even if the requests are not simultaneous. You can save time and space in FPGA VIs if you use the Arbitrate if Multiple Requestors Only arbitration option if the shared resource contains only one requestor in the entire FPGA VI hierarchy.
Use the Arbitrate if Multiple Requestors Only option in the following situations:
If you select the Never Arbitrate option for a resource interface, LabVIEW does not add arbitration components, which saves significant space on the FPGA. In addition to saving space, the Never Arbitrate option allows some of the FPGA I/O and FIFO functions to execute in a single clock cycle. However, in cases where there are multiple accessors, multiple signals will be combined into one signal, resulting in additional logic. To use the Never Arbitrate option, you must guarantee sequential access to the resource interface in the data flow of the FPGA VI, as shown in the following block diagram.
In the block diagram above, the Flat Sequence structure ensures that the two FIFO Method Nodes do not execute simultaneously, so resource contention does not occur. In such situations, Never Arbitrate is an appropriate option. However, if you select the Never Arbitrate option and make simultaneous requests, the behavior of the FPGA VI is undefined and data corruption is possible.
|Note To ensure data integrity, avoid reading or writing to the same FIFO by multiple objects, even if the access requests are not simultaneous.|
Selecting the Never Arbitrate option when simulating an FPGA application that contains memory items with multiple accessors may result in incorrect behavior. For example, if your application includes multiple writers, each writer can update the memory address specified during simulation. Additionally, if your application includes multiple readers, each reader can assess the memory address specified during simulation.