Understanding the LabVIEW FPGA Compile System (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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The LabVIEW FPGA compile system consists of three major components: LabVIEW, the compile server, and the compile worker. These three components have the following roles in compiling FPGA VIs into bitfiles to download to the FPGA chip on the target:

  • LabVIEW—Sends compile job requests to the compile server.
  • Compile server—Receives requests from LabVIEW and sends compile jobs to an available compile worker.
  • Compile worker—Takes job requests from the compile server and compiles the FPGA VI.

If you installed the LabVIEW FPGA Module and the Xilinx compilation tools on the same computer, this three-component architecture does not require any special configuration. By default, LabVIEW and the compile worker use the compile server installed on the local computer, called localhost. If you install the Xilinx compilation tools on a remote computer, you can compile the FPGA VI remotely using one or more remote compile workers.

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How the Compilation Process Works

The compilation time depends on the size of the VI, the processor speed, and the amount of memory in the computer on which you are compiling. If the computer does not have sufficient memory, smaller block diagrams might compile quickly, but larger block diagrams might use large amounts of virtual memory, which can cause compilations to fail or take over 10 times longer to complete.

The following steps outline the process of compiling FPGA VIs. LabVIEW displays compilation status in the Compilation Status window. You can view the different compilation reports if you are connected to the compile server.

  1. Generation of intermediate files—LabVIEW converts the FPGA VI into intermediate files (HDL code) to send to the compile server.
  2. Queuing—The compile server queues jobs and send the intermediate files to the compile worker for compiling.
  3. HDL compilation, analysis, and synthesis—The compile worker transforms intermediate files (HDL code) into digital logic elements.
  4. Mapping—The compile worker divides the application logic between the physical building blocks on the FPGA.
  5. Placing and routing—The compile worker assigns the logic to physical building blocks on the FPGA and routes the connections between the logic blocks to meet the space or timing constraints of the compilation.
  6. Generating programming file—The compile worker creates binary data that LabVIEW saves inside a bitfile.
  7. Creating bitfile—LabVIEW saves the bitfile in a subdirectory of the project directory and can download and/or run the application on the FPGA VI.

Related Information

Compilation Status Window

Reports Available from the Compilation Status Window

Compiling, Downloading, and Running FPGA VIs


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