|LabVIEW 2016 FPGA Module Help|
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|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
A test bench is a custom VI that provides some stimulus to the unit under test and reads back the results to verify the design. In this case, the unit under test is the FPGA VI. The test bench passes or fails depending on the response. A simple test bench includes two parts:
You can create a custom VI to simulate I/O in LabVIEW for use as a test bench for your FPGA VI. You can use a custom VI as a test bench to create the data coming from a particular input or monitor an output. For example, if the expected input for a particular component is a noisy sine wave, you can use a custom VI to create the noisy sine wave. Every time an FPGA VI reads an input by calling an FPGA I/O Node, LabVIEW uses the custom VI you specify to provide the data. Using custom VIs for FPGA I/O creates a repeatable scenario for testing and makes it possible to change the data for a particular input. For example, if you need a square wave instead of a sine wave, you can modify the custom VI. You also can use custom VIs for FPGA I/O to monitor an output from FPGA I/O Nodes. For example, if the expected output of a component is a sine wave and the frequency of the sine wave is the important aspect of the output, you can create a custom VI to monitor the output of an FPGA I/O Node to verify that the frequency is correct.
Before debugging an FPGA VI using a test bench, you can test the logic of the VI without compiling it by executing the FPGA VI in simulation mode using simulated I/O. Executing an FPGA VI in simulation mode using simulated I/O saves compilation time, makes tests easier to repeat, and decreases the number of modifications necessary to create a test bench for additional debugging.
Complete the following steps to create a custom VI test bench from a template.
Refer to the Tutorial: Creating Test Benches topic for an example of how to create and use a custom VI test bench.