|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Every FPGA chip, or FPGA, is composed of a finite number of predefined resources with programmable interconnects. These interconnects implement the digital circuit you design with the LabVIEW FPGA Module. When you create an FPGA VI, you design a circuit schematic that describes how logic blocks are wired together on the FPGA. When you compile the VI, the compilation tools translate the FPGA VI into the FPGA circuit.
|Note This topic contains low-level FPGA implementation concepts. You do not need to understand these concepts to get started with the LabVIEW FPGA Module, but understanding them can help you build more efficient FPGA VIs.|
The following illustration shows the relationship between logic blocks, I/O blocks, and programmable routing on an FPGA.
The following FPGA specifications are important to consider when designing an FPGA application.
Refer to the support document at ni.com for more information about the fundamental parts of the FPGA.
FPGA resources are resources on the FPGA that can perform logic functions. FPGA resources are grouped in slices to create configurable logic blocks. A slice contains a set number of LUTs, flip-flops and multiplexers. A LUT is a collection of logic gates hard-wired on the FPGA. LUTs store a predefined list of outputs for every combination of inputs and provide a fast way to retrieve the output of a logic operation. A flip-flop is a circuit capable of two stable states and represents a single bit. A multiplexer, also known as a mux, is a circuit that selects between two or more inputs and outputs the selected input.
Different FPGA families implement slices and LUTs differently. For example, a slice on a Virtex-II FPGA has two LUTs and two flip-flops but a slice on a Virtex-5 FPGA has four LUTs and four flip-flops. In addition, the number of inputs to a LUT, commonly two to six, depend on the FPGA family.
A register is a group of flip-flops that stores a bit pattern. A register on the FPGA has a clock, input data, output data, and enable signal port. Every clock cycle, the input data is latched, stored internally, and the output data is updated to match the internally stored data. FPGA VIs use registers to perform the following functions:
Registers are a key concept in understanding timing considerations for FPGA VIs.
Block RAM, or block memory, is RAM that is embedded throughout the FPGA for storing data. In general, LabVIEW uses block RAM when synthesizing Memory & FIFO functions. You can specify how LabVIEW implements FIFOs and memory items using the FIFO Properties and Memory Properties dialog boxes, respectively.