CLIP Tutorial, Part 1: Creating VHDL Code (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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To add component-level IP (CLIP) to an FPGA target, you must provide IP, in the form of VHDL code, to compile into the FPGA target.

The tutorial uses a 16-bit adder with a flip-flop.

The following VHDL code takes two I16 numeric values and returns their sum as an I16 numeric value. The VHDL code also requires a clock and a reset signal from the FPGA Module. If you want to use this example code, copy the code to a text file and save the file as DemoClipAdder.vhd.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity DemoClipAdder is
    port (
          clk : in std_logic;
          aReset : in std_logic;
          cPortA : in std_logic_vector(15 downto 0);
          cPortB : in std_logic_vector(15 downto 0);
          cAddOut : out std_logic_vector(15 downto 0) := (others => '0')
end DemoClipAdder;

architecture rtl of DemoClipAdder is
    process(aReset, clk) begin
      if(aReset = '1') then
        cAddOut <= (others => '0');
      elsif rising_edge(clk) then
        cAddOut <= std_logic_vector(signed(cPortA) + signed(cPortB));
      end if;
    end process;
end rtl;

Adding Constraints to CLIP

The following UCF code constrains the clock rate of the sum output to be no less than 100 MHz. If you want to use this example code, copy the code to a text file and save the file as (Xilinx ISE) DemoClipAdder.ucf or (Xilinx Vivado) DemoClipAdder.xdc. Add this constraints file along with the VHD file as synthesis files in the Configuring CLIP wizard to implement this constraint.

(Xilinx ISE)

NET "%ClipInstancePath%/cAddOut*" TNM_NET = %ClipInstanceName%AddOut;
TIMESPEC TS_%ClipInstanceName%ThruAdder = TO "%ClipInstanceName%AddOut" 10 ns;

(Xilinx Vivado)

create_clock -period 10.000 -name %ClipInstanceName%Clk -waveform {0.000 5.000} -add [get_pins %ClipInstancePath%/clk]
set_clock_latency -clock [get_clocks {%ClipInstanceName%CLK}] 10.0 [get_pins {%ClipInstancePath%/cAddOut[0]}]

Previous: CLIP Tutorial: Adding Component-Level IP to an FPGA Project Next: CLIP Tutorial, Part 2: Defining the Interface


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